From owner-freebsd-hackers@FreeBSD.ORG Thu Jul 29 20:03:03 2010 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 64BA71065789 for ; Thu, 29 Jul 2010 20:03:03 +0000 (UTC) (envelope-from babkin@verizon.net) Received: from vms173019pub.verizon.net (vms173019pub.verizon.net [206.46.173.19]) by mx1.freebsd.org (Postfix) with ESMTP id 3B4DD8FC08 for ; Thu, 29 Jul 2010 20:03:03 +0000 (UTC) Received: from vms170009.mailsrvcs.net ([unknown] [172.18.12.132]) by vms173019.mailsrvcs.net (Sun Java(tm) System Messaging Server 7u2-7.02 32bit (built Apr 16 2009)) with ESMTPA id <0L6C00J6E50W3RW1@vms173019.mailsrvcs.net> for freebsd-hackers@freebsd.org; Thu, 29 Jul 2010 15:02:58 -0500 (CDT) Received: from 130.214.17.1 ([130.214.17.1]) by vms170009.mailsrvcs.net (Verizon Webmail) with HTTP; Thu, 29 Jul 2010 15:02:56 -0500 (CDT) Date: Thu, 29 Jul 2010 15:02:56 -0500 (CDT) From: Sergey Babkin To: avg@icyb.net.ua Message-id: <382607918.1356296.1280433776963.JavaMail.root@vms170009.mailsrvcs.net> MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: quoted-printable X-Originating-IP: [130.214.17.1] X-Mailman-Approved-At: Thu, 29 Jul 2010 20:13:59 +0000 Cc: freebsd-hackers@freebsd.org, pebu3op@googlemail.com Subject: Re: Re: coherence-problem on the mapped memory buffer X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Jul 2010 20:03:03 -0000 Jul 29, 2010 12:58:07 PM, avg@icyb.net.ua wrote: >on 29/07/2010 19:13 Andriy Gapon said the following: >> on 29/07/2010 17:13 Alexander Fiveg said the following: >In fact I have a suspicion that the problem might have to do with multiple >mappings of the shared pages, but far from sure... >Take a look at Intel=C2=AE 64 and IA-32 Architectures Software Developer= =E2=80=99s Manual >Volume 3A - System Programming Guide, Part 1; Chapter 11.12.4 Programming = the PAT; >starting at the following words: >=C2=ABThe PAT allows any memory type to be specified in the page tables, a= nd therefore >it is possible to have a single physical page mapped to two or more differ= ent >linear addresses, each with different memory types. Intel does not support= this >practice...=C2=BB My guess would be that the memory type is not marked as DMA-capable. AFAIK = the Intel CPUs do the hardware snooping on the physical addresses, so they have no coheren= cy issues benween=20 themselves. However if a DMA writer changes the memory, this I think does n= ot get normally=20 propagated to the front-side bus, and the CPUs would not see it. You may ne= ed to either explicitly flush the CPU cache before accessing these pages or mark them as= non-cacheable. -SB