From owner-svn-src-head@freebsd.org Sat Oct 28 16:50:25 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 28B6AE47E3A; Sat, 28 Oct 2017 16:50:25 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id EBFAA74A6F; Sat, 28 Oct 2017 16:50:24 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v9SGoOQr052523; Sat, 28 Oct 2017 16:50:24 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v9SGoOcY052522; Sat, 28 Oct 2017 16:50:24 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201710281650.v9SGoOcY052522@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Sat, 28 Oct 2017 16:50:24 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r325054 - head/sys/dev/ffec X-SVN-Group: head X-SVN-Commit-Author: ian X-SVN-Commit-Paths: head/sys/dev/ffec X-SVN-Commit-Revision: 325054 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 28 Oct 2017 16:50:25 -0000 Author: ian Date: Sat Oct 28 16:50:23 2017 New Revision: 325054 URL: https://svnweb.freebsd.org/changeset/base/325054 Log: Increase the alignment of the rx/tx descriptor ring buffers to 64 bytes. 16 was the correct alignment for older hardware, but the imx7 requires 64-byte alignment, which is a fine value to use on all systems. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de Modified: head/sys/dev/ffec/if_ffecreg.h Modified: head/sys/dev/ffec/if_ffecreg.h ============================================================================== --- head/sys/dev/ffec/if_ffecreg.h Sat Oct 28 07:06:57 2017 (r325053) +++ head/sys/dev/ffec/if_ffecreg.h Sat Oct 28 16:50:23 2017 (r325054) @@ -317,7 +317,7 @@ struct ffec_hwdesc * The hardware imposes alignment restrictions on various objects involved in * DMA transfers. These values are expressed in bytes (not bits). */ -#define FEC_DESC_RING_ALIGN 16 +#define FEC_DESC_RING_ALIGN 64 #define FEC_RXBUF_ALIGN 16 #define FEC_TXBUF_ALIGN 16