From owner-freebsd-arch@FreeBSD.ORG Thu Oct 25 16:30:16 2012 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id A0207307 for ; Thu, 25 Oct 2012 16:30:16 +0000 (UTC) (envelope-from oppermann@networx.ch) Received: from c00l3r.networx.ch (c00l3r.networx.ch [62.48.2.2]) by mx1.freebsd.org (Postfix) with ESMTP id 007E68FC16 for ; Thu, 25 Oct 2012 16:30:15 +0000 (UTC) Received: (qmail 42256 invoked from network); 25 Oct 2012 18:07:52 -0000 Received: from c00l3r.networx.ch (HELO [127.0.0.1]) ([62.48.2.2]) (envelope-sender ) by c00l3r.networx.ch (qmail-ldap-1.03) with SMTP for ; 25 Oct 2012 18:07:52 -0000 Message-ID: <5089690A.8070503@networx.ch> Date: Thu, 25 Oct 2012 18:30:02 +0200 From: Andre Oppermann User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:16.0) Gecko/20121010 Thunderbird/16.0.1 MIME-Version: 1.0 To: John Baldwin Subject: Re: CACHE_LINE_SIZE on x86 References: <201210250918.00602.jhb@freebsd.org> In-Reply-To: <201210250918.00602.jhb@freebsd.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: Jim Harris , freebsd-arch@freebsd.org X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Oct 2012 16:30:16 -0000 On 25.10.2012 15:18, John Baldwin wrote: > On Wednesday, October 24, 2012 3:13:38 pm Jim Harris wrote: >> While investigating padding of the ULE scheduler locks (r242014), I >> recently discovered that CACHE_LINE_SIZE on x86 is defined as 128 (not >> 64). From what I can tell from svn logs, this was to account for 128 >> byte cache "sectors" that existed on the NetBurst micro architecture >> CPUs. >> >> I'm curious if there's been consideration in changing this back to 64? >> With maybe a kernel config option to modify it? On 2S systems (but >> not on 1S systems), I see a benefit using CACHE_LINE_SIZE=128 for the >> scheduler locks. I suspect this is related to data prefetching but am >> still running experiments to verify. > > All the i7 and later systems I've seen (maybe even Penryn?) have a BIOS option > (typically enabled by default) to enable adjacent cache line prefetching (my > understanding is that this only affects the LLC, and it seems to always fetch > an aligned 128 bytes, so if your miss is in the "second" line it fetches N-1 > and N, not always fetching N and N+1). That is why I thought we still use 128 > bytes on x86. As long as the additionally prefetched cache line has its own MOESI state and gets marked as shared there is not problem with using only 64B alignment and padding. -- Andre