From owner-svn-src-head@FreeBSD.ORG Sat Dec 1 00:56:20 2012 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 0A5D6629; Sat, 1 Dec 2012 00:56:20 +0000 (UTC) (envelope-from jkim@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id D6EBF8FC0C; Sat, 1 Dec 2012 00:56:19 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.5/8.14.5) with ESMTP id qB10uJ3x091653; Sat, 1 Dec 2012 00:56:19 GMT (envelope-from jkim@svn.freebsd.org) Received: (from jkim@localhost) by svn.freebsd.org (8.14.5/8.14.5/Submit) id qB10uJY2091651; Sat, 1 Dec 2012 00:56:19 GMT (envelope-from jkim@svn.freebsd.org) Message-Id: <201212010056.qB10uJY2091651@svn.freebsd.org> From: Jung-uk Kim Date: Sat, 1 Dec 2012 00:56:19 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r243737 - in head/sys: amd64/pci i386/pci X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Dec 2012 00:56:20 -0000 Author: jkim Date: Sat Dec 1 00:56:19 2012 New Revision: 243737 URL: http://svnweb.freebsd.org/changeset/base/243737 Log: Remove duplicate code. Reduce diff between amd64 and i386. Modified: head/sys/amd64/pci/pci_cfgreg.c head/sys/i386/pci/pci_cfgreg.c Modified: head/sys/amd64/pci/pci_cfgreg.c ============================================================================== --- head/sys/amd64/pci/pci_cfgreg.c Sat Dec 1 00:11:24 2012 (r243736) +++ head/sys/amd64/pci/pci_cfgreg.c Sat Dec 1 00:56:19 2012 (r243737) @@ -295,6 +295,13 @@ pcie_cfgregopen(uint64_t base, uint8_t m return (1); } +#define PCIE_VADDR(base, reg, bus, slot, func) \ + ((base) + \ + ((((bus) & 0xff) << 20) | \ + (((slot) & 0x1f) << 15) | \ + (((func) & 0x7) << 12) | \ + ((reg) & 0xfff))) + /* * AMD BIOS And Kernel Developer's Guides for CPU families starting with 10h * have a requirement that all accesses to the memory mapped PCI configuration @@ -302,12 +309,6 @@ pcie_cfgregopen(uint64_t base, uint8_t m * Since other vendors do not currently have any contradicting requirements * the AMD access pattern is applied universally. */ -#define PCIE_VADDR(base, reg, bus, slot, func) \ - ((base) + \ - ((((bus) & 0xff) << 20) | \ - (((slot) & 0x1f) << 15) | \ - (((func) & 0x7) << 12) | \ - ((reg) & 0xfff))) static int pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg, Modified: head/sys/i386/pci/pci_cfgreg.c ============================================================================== --- head/sys/i386/pci/pci_cfgreg.c Sat Dec 1 00:11:24 2012 (r243736) +++ head/sys/i386/pci/pci_cfgreg.c Sat Dec 1 00:56:19 2012 (r243737) @@ -610,25 +610,29 @@ pcie_cfgregopen(uint64_t base, uint8_t m } #endif /* !XEN */ -#define PCIE_PADDR(bar, reg, bus, slot, func) \ - ((bar) | \ - (((bus) & 0xff) << 20) | \ +#define PCIE_PADDR(base, reg, bus, slot, func) \ + ((base) + \ + ((((bus) & 0xff) << 20) | \ (((slot) & 0x1f) << 15) | \ (((func) & 0x7) << 12) | \ - ((reg) & 0xfff)) + ((reg) & 0xfff))) -/* - * Find an element in the cache that matches the physical page desired, or - * create a new mapping from the least recently used element. - * A very simple LRU algorithm is used here, does it need to be more - * efficient? - */ -static __inline struct pcie_cfg_elem * -pciereg_findelem(vm_paddr_t papage) +static __inline vm_offset_t +pciereg_findaddr(int bus, unsigned slot, unsigned func, unsigned reg) { struct pcie_cfg_list *pcielist; struct pcie_cfg_elem *elem; + vm_paddr_t pa, papage; + pa = PCIE_PADDR(pcie_base, reg, bus, slot, func); + papage = pa & ~PAGE_MASK; + + /* + * Find an element in the cache that matches the physical page desired, + * or create a new mapping from the least recently used element. + * A very simple LRU algorithm is used here, does it need to be more + * efficient? + */ pcielist = &pcie_list[PCPU_GET(cpuid)]; TAILQ_FOREACH(elem, pcielist, elem) { if (elem->papage == papage) @@ -649,7 +653,7 @@ pciereg_findelem(vm_paddr_t papage) TAILQ_REMOVE(pcielist, elem, elem); TAILQ_INSERT_HEAD(pcielist, elem, elem); } - return (elem); + return (elem->vapage | (pa & PAGE_MASK)); } /* @@ -664,9 +668,7 @@ static int pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg, unsigned bytes) { - struct pcie_cfg_elem *elem; vm_offset_t va; - vm_paddr_t pa, papage; int data = -1; if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX || @@ -674,10 +676,7 @@ pciereg_cfgread(int bus, unsigned slot, return (-1); critical_enter(); - pa = PCIE_PADDR(pcie_base, reg, bus, slot, func); - papage = pa & ~PAGE_MASK; - elem = pciereg_findelem(papage); - va = elem->vapage | (pa & PAGE_MASK); + va = pciereg_findaddr(bus, slot, func, reg); switch (bytes) { case 4: @@ -702,19 +701,14 @@ static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data, unsigned bytes) { - struct pcie_cfg_elem *elem; vm_offset_t va; - vm_paddr_t pa, papage; if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX) return; critical_enter(); - pa = PCIE_PADDR(pcie_base, reg, bus, slot, func); - papage = pa & ~PAGE_MASK; - elem = pciereg_findelem(papage); - va = elem->vapage | (pa & PAGE_MASK); + va = pciereg_findaddr(bus, slot, func, reg); switch (bytes) { case 4: