From owner-svn-src-user@FreeBSD.ORG Wed Sep 28 15:36:09 2011 Return-Path: Delivered-To: svn-src-user@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 28DBC106564A; Wed, 28 Sep 2011 15:36:09 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 17D1F8FC08; Wed, 28 Sep 2011 15:36:09 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p8SFa845079431; Wed, 28 Sep 2011 15:36:08 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p8SFa8Ig079429; Wed, 28 Sep 2011 15:36:08 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201109281536.p8SFa8Ig079429@svn.freebsd.org> From: Adrian Chadd Date: Wed, 28 Sep 2011 15:36:08 +0000 (UTC) To: src-committers@freebsd.org, svn-src-user@freebsd.org X-SVN-Group: user MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r225842 - user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416 X-BeenThere: svn-src-user@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the experimental " user" src tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Sep 2011 15:36:09 -0000 Author: adrian Date: Wed Sep 28 15:36:08 2011 New Revision: 225842 URL: http://svn.freebsd.org/changeset/base/225842 Log: Flip back to the atheros defaults for now. Now that I've figured out why I'm getting performance issues on these mips boards (interrupts occuring in a race window between critical_enter and "wait", and thus being delayed until the next interrupt), this provides better RX performance under heavy UDP load. This doesn't fix the issue - it just means that under heavy UDP load, I'm not getting 1 RX interrupt every 2ms. This turns out not to be often enough in some occasional situations. Some more research is needed though.. Modified: user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Modified: user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c ============================================================================== --- user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Wed Sep 28 15:01:20 2011 (r225841) +++ user/adrian/if_ath_tx/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Wed Sep 28 15:36:08 2011 (r225842) @@ -361,8 +361,8 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMO OS_REG_WRITE(ah, AR_MIRT, 0); #ifdef AH_AR5416_INTERRUPT_MITIGATION - OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); - OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); + OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 250); + OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 700); #endif ar5416InitBB(ah, chan);