From owner-svn-src-head@freebsd.org Sat Oct 28 17:30:51 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 0FE2BE48B92; Sat, 28 Oct 2017 17:30:51 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id CC78675C50; Sat, 28 Oct 2017 17:30:50 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v9SHUnj4069108; Sat, 28 Oct 2017 17:30:49 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v9SHUnj4069107; Sat, 28 Oct 2017 17:30:49 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201710281730.v9SHUnj4069107@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Sat, 28 Oct 2017 17:30:49 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r325056 - head/sys/dev/ffec X-SVN-Group: head X-SVN-Commit-Author: ian X-SVN-Commit-Paths: head/sys/dev/ffec X-SVN-Commit-Revision: 325056 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 28 Oct 2017 17:30:51 -0000 Author: ian Date: Sat Oct 28 17:30:49 2017 New Revision: 325056 URL: https://svnweb.freebsd.org/changeset/base/325056 Log: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7. When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de Modified: head/sys/dev/ffec/if_ffec.c Modified: head/sys/dev/ffec/if_ffec.c ============================================================================== --- head/sys/dev/ffec/if_ffec.c Sat Oct 28 17:06:13 2017 (r325055) +++ head/sys/dev/ffec/if_ffec.c Sat Oct 28 17:30:49 2017 (r325056) @@ -1639,8 +1639,21 @@ ffec_attach(device_t dev) /* Try to get the MAC address from the hardware before resetting it. */ ffec_get_hwaddr(sc, eaddr); - /* Reset the hardware. Disables all interrupts. */ - WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); + /* + * Reset the hardware. Disables all interrupts. + * + * When the FEC is connected to the AXI bus (indicated by AVB flag), a + * MAC reset while a bus transaction is pending can hang the bus. + * Instead of resetting, turn off the ENABLE bit, which allows the + * hardware to complete any in-progress transfers (appending a bad CRC + * to any partial packet) and release the AXI bus. This could probably + * be done unconditionally for all hardware variants, but that hasn't + * been tested. + */ + if (sc->fectype & FECFLAG_AVB) + WR4(sc, FEC_ECR_REG, 0); + else + WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); /* Setup interrupt handler. */ error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,