From owner-freebsd-mips@FreeBSD.ORG Mon Aug 27 15:20:53 2012 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id B44911065673; Mon, 27 Aug 2012 15:20:53 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-pz0-f54.google.com (mail-pz0-f54.google.com [209.85.210.54]) by mx1.freebsd.org (Postfix) with ESMTP id 7601A8FC15; Mon, 27 Aug 2012 15:20:53 +0000 (UTC) Received: by dadr6 with SMTP id r6so2589280dad.13 for ; Mon, 27 Aug 2012 08:20:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=lYrRM128qw04nZGkoy9WgB67sDTxSyD1vHe6xtBexvo=; b=ajYXEeB64Q8sgiJvPDcQkhcYLTpxX+4bxS1dk9blsyBAxhjVkMd5u5tSfiEPg7RmSB kc8Sq1JfWh/cI6jIinuo7tNbnfvkeC3SKBjbZXooJrfhgc9uBHpGQGHhpkO5lyCSkCQ2 i2zMmX8uspoG9YByjg9qYniJdsrthFCXhu7Da/k+7t4xFilPiFrwEIM8OhyYqW0NAxve 1z6Ug3KtaAIRG1Kx7fBG39DhO0ixteho3n4n+m1axU6wpj9gq30F7D+cW3RD9mM8F525 BQ+vOw8oW9uVElLkOygvPFmbcJqyX1TOotxbUMEBtAGyzQWZGau6A9Dy41T+0Husyp83 eoQg== MIME-Version: 1.0 Received: by 10.68.129.131 with SMTP id nw3mr35286569pbb.43.1346080853000; Mon, 27 Aug 2012 08:20:53 -0700 (PDT) Sender: adrian.chadd@gmail.com Received: by 10.68.36.106 with HTTP; Mon, 27 Aug 2012 08:20:52 -0700 (PDT) In-Reply-To: References: <6D83AF9D-577B-4C83-84B7-C4E3B32695FC@bsdimp.com> Date: Mon, 27 Aug 2012 08:20:52 -0700 X-Google-Sender-Auth: ohyisdNkmhbkzwukiyHFrt829tI Message-ID: From: Adrian Chadd To: Tim Kientzle Content-Type: text/plain; charset=ISO-8859-1 Cc: Hans Petter Selasky , freebsd-arm@freebsd.org, freebsd-mips@freebsd.org, freebsd-arch@freebsd.org Subject: Re: Partial cacheline flush problems on ARM and MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Aug 2012 15:20:53 -0000 On 27 August 2012 08:12, Tim Kientzle wrote: >> No. I don't think so. the reason is that you can't define USB_DMA_ALGIN to be a constant on MIPS, at least, or I think ARM because that's determined at run time. FYI, I wonder if MIPS may need some run time value for that. Right now we hide it behind needing a custom config file for each mips variant, rather than supporting one mips24k kernel for ${LOTS} of variants. > But don't mbuf structures do pretty much what Hans is suggesting? > > Why is mbuf okay? Which part of mbufs? I think the difference here is that there's no concurrent access. Ie, although you may have an mbuf header + data inside the same cache line, you wouldn't go fondling the mbuf once it's handed to the hardware. But I was under the impression that mbuf + mbuf buffers are already correctly aligned. This all honestly looks like a very i386-centric interpretation of the busdma "intention", which I think illustrates a need to better document what assumptions busdma actually makes. That does remind me, I think the ath(4) driver does the same (since it allocates its own descriptor block and then treats it as an array of descriptors for the hardware to access) - I should ensure that sizeof(ath_desc) is aligned on the relevant architecture. It gets slightly scary - AR93xx TX descriptors are "L1 cache == 128 byte aligned" which is an enormous waste of memory compared to a 16 or 32 byte aligned platform. Alas.. Adrian