From owner-freebsd-hackers@FreeBSD.ORG Sun Sep 18 19:19:48 2011 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 81CC81065675 for ; Sun, 18 Sep 2011 19:19:48 +0000 (UTC) (envelope-from lacombar@gmail.com) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx1.freebsd.org (Postfix) with ESMTP id E36178FC16 for ; Sun, 18 Sep 2011 19:19:47 +0000 (UTC) Received: by wwe3 with SMTP id 3so6621440wwe.31 for ; Sun, 18 Sep 2011 12:19:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=R7ebOu4yv+tlzxqTnvGuLdaRJwAQrAlYwKudFQSThTA=; b=Ej/wgdOET1FKJx1cVtd/JWf0tSi8GXfU856A7XGJCsfCgItAZvnczbUrLkM6Wd9ojI Trz063893W/gvIMGJGXQnntdL1RZN5GU4gfcOa6RbFk58Aq6bpr/5oBUZr+PHNmXDgng htlUX6XobCHcqeM+gYckKifiopiVS7QaA+mds= MIME-Version: 1.0 Received: by 10.227.175.77 with SMTP id w13mr1787920wbz.53.1316373586716; Sun, 18 Sep 2011 12:19:46 -0700 (PDT) Received: by 10.180.95.169 with HTTP; Sun, 18 Sep 2011 12:19:46 -0700 (PDT) In-Reply-To: <20110917203218.GC13993@michelle.cdnetworks.com> References: <4E744BCE.7060302@sepehrs.com> <20110917203218.GC13993@michelle.cdnetworks.com> Date: Sun, 18 Sep 2011 15:19:46 -0400 Message-ID: From: Arnaud Lacombe To: jfv@freebsd.org Content-Type: text/plain; charset=ISO-8859-1 Cc: pyunyh@gmail.com, freebsd-hackers@freebsd.org, Hooman Fazaeli Subject: Re: intel checksum offload X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 18 Sep 2011 19:19:48 -0000 Hi, On Sat, Sep 17, 2011 at 4:32 PM, YongHyeon PYUN wrote: > On Sat, Sep 17, 2011 at 11:57:10AM +0430, Hooman Fazaeli wrote: >> Hi list, >> >> The data sheet for intel 82576 advertises IP TX/RX checksum offload >> but the driver does not set CSUM_IP in ifp->if_hwassist. Does this mean that >> driver (and chip) do not support IP TX checksum offload or the support for >> TX is not yet included in the driver? > > After reading this mail, I checked em(4)/lem(4) code and noticed > these drivers removed CSUM_IP capability as well. igb(4) didn't > support CSUM_IP from day 1 but em(4)/lem(4) used to take advantage > of IP checksum offloading capability. > Given that these drivers share many code with Linux, Jack may know > the details and why IP checksum offloading code was removed. Note, > Linux does not use IP checksum offloading so I guess this could be > oversight in shared code. > > BTW, hackers may not be right ML to post this kind of post. > CCed to jfv@, the driver maintainer. > This is slightly off-topic, but still.. FWIW, I'm not really impressed by what chips claim to support vs. what has been implemented in the driver. As per the product brief, the 82574 supports multiqueue (at least should support up to 5 MSI-X vectors, 2 RX and 2 TX), but this support was removed from em(4) in mid-2010[0]. Also, the 82571 and the 82574 should also support header split, but this is currently only implemented in igb(4), not em(4). - Arnaud [0]: the commit message say "performance was not good", but it is not the driver's developer to decide whether or not a feature is good or not. The developer's job is to implement the chip capabilities, and let it to the user to enable or disable the capabilities. At best, the developer can decide whether or not to enable the feature by default.