From nobody Mon May 12 12:50:26 2025 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Zwzwg37qVz5w0Sw; Mon, 12 May 2025 12:50:27 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R11" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Zwzwf61pmz3rGL; Mon, 12 May 2025 12:50:26 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1747054226; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=FrSajnEU5PcaZK67XCcx3bv1w/rUEg0wnSYvpFtyW7E=; b=aS7HibxSw4V0asPlU96eJ71FaZCORtW+Mt29frf8TUyKNsTpIHV0rzXOeZmMroDqWT1lhH +y8oc/olSdjPfiO4DwL9conPZD6rjdpox0HwdRQOSMPWX4zdKdjn1J4a4JzmWQnuDKmk2V yB2+Pfp4c2vZe8FnkiDzC9N7ms9Cmw07s+dILvVpGi6CIsXxYMrQ888xaiaUtydaPFwwfr HoTo1OYjqLsUB0vQkqctqNswCy1F+pMg4K8lAzJafV4wqBlRM5V28/dCWxi8vDDGJLlZzk GHol/Pau6j3717y67/aa0z04BVOIZxPunGSOeP34U9vgKvD1oleq7tMJtg8hEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1747054226; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=FrSajnEU5PcaZK67XCcx3bv1w/rUEg0wnSYvpFtyW7E=; b=IvB29nsZZOCPu2QFFDNFZoukPYvhIv/pSYFTX5r3H3owyh+s9ZNd1C4nF42hCWYot2bB42 D3+Mbn9e52Jhuoc1+XM/6tdFcysAHCCBaZ8JSoKlEEn0zy0l16BJLNsGAu1Fmx9Mln+uTI P2/aPrYc7XcqVw/EbrXezzsYgwyALSb0NQ/5m+8vJVMgLXQXHzD1aNdgyrGXkWXISaGzDg PDhuVHy9Vzbv8NYCNFAOF7KjfH9JSMAdqwgjOUbn3czSnBSKoMDQLlmaGDMrqm3lC2Us7Q yMuYUgKL4LAHT65TSWj50Hgvcz7rJXCdtB3ZeJQvwVLWVIu71iBEMLSgwuPPTQ== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1747054226; a=rsa-sha256; cv=none; b=W/c6Uk5t/reZoATa9km4V19jZ5lY3pp4Vk9yIVQDufK5DJL+wnvx0WoT7GICmTFhWkwaFV YAHyM51EZyETysTftdht3jZxkITMkLnXeXpXzL4ALlI+7V/BkPj3r1s1fdHSUpmePaqtsx qlL06jafuoIAokOzlm7XgFKlrxM2kiAL4gh1tpi5gvI64wM0+l6wCRkYO/aRlyK4XwwuHV 6DLA8W4mblxkXncbjq/LILAv0aZNLMP8VDldHKL1lKNN3BTSO7KxfV1ObTAYwy90SPipRR idzZPRiGn0pTu7dOLPFsDUFWlrFmZFoRkcdcIuiO9x/UCiL4sg8Ee1PLlYdJtA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4Zwzwf5Tj7z1G4J; Mon, 12 May 2025 12:50:26 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 54CCoQeU083035; Mon, 12 May 2025 12:50:26 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 54CCoQtV083032; Mon, 12 May 2025 12:50:26 GMT (envelope-from git) Date: Mon, 12 May 2025 12:50:26 GMT Message-Id: <202505121250.54CCoQtV083032@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: e4619b088dd0 - main - arm64: Add the ESR ISS value to struct mrs_user_reg List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: e4619b088dd0853a3cf0841235d9576179b94d5b Auto-Submitted: auto-generated The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=e4619b088dd0853a3cf0841235d9576179b94d5b commit e4619b088dd0853a3cf0841235d9576179b94d5b Author: Andrew Turner AuthorDate: 2025-05-12 11:07:03 +0000 Commit: Andrew Turner CommitDate: 2025-05-12 11:07:03 +0000 arm64: Add the ESR ISS value to struct mrs_user_reg This will be used to compare against the ISS value from MSR/MRS exceptions. Reviewed by: harry.moulton_arm.com Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D50210 --- sys/arm64/arm64/identcpu.c | 2 ++ sys/arm64/include/armreg.h | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index 663c1a335114..c4eaaaafc279 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -2193,6 +2193,7 @@ static const struct mrs_field mvfr1_fields[] = { struct mrs_user_reg { u_int reg; + u_int iss; u_int CRm; u_int Op2; bool is64bit; @@ -2203,6 +2204,7 @@ struct mrs_user_reg { #define USER_REG(name, field_name, _is64bit) \ { \ .reg = name, \ + .iss = name##_ISS, \ .CRm = name##_CRm, \ .Op2 = name##_op2, \ .offset = __offsetof(struct cpu_desc, field_name), \ diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 8691e4b89649..a7950092048d 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -368,6 +368,7 @@ /* CTR_EL0 - Cache Type Register */ #define CTR_EL0 MRS_REG(CTR_EL0) #define CTR_EL0_REG MRS_REG_ALT_NAME(CTR_EL0) +#define CTR_EL0_ISS ISS_MSR_REG(CTR_EL0) #define CTR_EL0_op0 3 #define CTR_EL0_op1 3 #define CTR_EL0_CRn 0 @@ -768,6 +769,7 @@ /* ID_AA64AFR0_EL1 */ #define ID_AA64AFR0_EL1 MRS_REG(ID_AA64AFR0_EL1) #define ID_AA64AFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR0_EL1) +#define ID_AA64AFR0_EL1_ISS ISS_MSR_REG(ID_AA64AFR0_EL1) #define ID_AA64AFR0_EL1_op0 3 #define ID_AA64AFR0_EL1_op1 0 #define ID_AA64AFR0_EL1_CRn 0 @@ -777,6 +779,7 @@ /* ID_AA64AFR1_EL1 */ #define ID_AA64AFR1_EL1 MRS_REG(ID_AA64AFR1_EL1) #define ID_AA64AFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64AFR1_EL1) +#define ID_AA64AFR1_EL1_ISS ISS_MSR_REG(ID_AA64AFR1_EL1) #define ID_AA64AFR1_EL1_op0 3 #define ID_AA64AFR1_EL1_op1 0 #define ID_AA64AFR1_EL1_CRn 0 @@ -786,6 +789,7 @@ /* ID_AA64DFR0_EL1 */ #define ID_AA64DFR0_EL1 MRS_REG(ID_AA64DFR0_EL1) #define ID_AA64DFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR0_EL1) +#define ID_AA64DFR0_EL1_ISS ISS_MSR_REG(ID_AA64DFR0_EL1) #define ID_AA64DFR0_EL1_op0 3 #define ID_AA64DFR0_EL1_op1 0 #define ID_AA64DFR0_EL1_CRn 0 @@ -893,6 +897,7 @@ /* ID_AA64DFR1_EL1 */ #define ID_AA64DFR1_EL1 MRS_REG(ID_AA64DFR1_EL1) #define ID_AA64DFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR1_EL1) +#define ID_AA64DFR1_EL1_ISS ISS_MSR_REG(ID_AA64DFR1_EL1) #define ID_AA64DFR1_EL1_op0 3 #define ID_AA64DFR1_EL1_op1 0 #define ID_AA64DFR1_EL1_CRn 0 @@ -920,6 +925,7 @@ /* ID_AA64ISAR0_EL1 */ #define ID_AA64ISAR0_EL1 MRS_REG(ID_AA64ISAR0_EL1) #define ID_AA64ISAR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR0_EL1) +#define ID_AA64ISAR0_EL1_ISS ISS_MSR_REG(ID_AA64ISAR0_EL1) #define ID_AA64ISAR0_EL1_op0 3 #define ID_AA64ISAR0_EL1_op1 0 #define ID_AA64ISAR0_EL1_CRn 0 @@ -1022,6 +1028,7 @@ /* ID_AA64ISAR1_EL1 */ #define ID_AA64ISAR1_EL1 MRS_REG(ID_AA64ISAR1_EL1) #define ID_AA64ISAR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR1_EL1) +#define ID_AA64ISAR1_EL1_ISS ISS_MSR_REG(ID_AA64ISAR1_EL1) #define ID_AA64ISAR1_EL1_op0 3 #define ID_AA64ISAR1_EL1_op1 0 #define ID_AA64ISAR1_EL1_CRn 0 @@ -1141,6 +1148,7 @@ /* ID_AA64ISAR2_EL1 */ #define ID_AA64ISAR2_EL1 MRS_REG(ID_AA64ISAR2_EL1) #define ID_AA64ISAR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR2_EL1) +#define ID_AA64ISAR2_EL1_ISS ISS_MSR_REG(ID_AA64ISAR2_EL1) #define ID_AA64ISAR2_EL1_op0 3 #define ID_AA64ISAR2_EL1_op1 0 #define ID_AA64ISAR2_EL1_CRn 0 @@ -1226,6 +1234,7 @@ /* ID_AA64MMFR0_EL1 */ #define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1) #define ID_AA64MMFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR0_EL1) +#define ID_AA64MMFR0_EL1_ISS ISS_MSR_REG(ID_AA64MMFR0_EL1) #define ID_AA64MMFR0_EL1_op0 3 #define ID_AA64MMFR0_EL1_op1 0 #define ID_AA64MMFR0_EL1_CRn 0 @@ -1333,6 +1342,7 @@ /* ID_AA64MMFR1_EL1 */ #define ID_AA64MMFR1_EL1 MRS_REG(ID_AA64MMFR1_EL1) #define ID_AA64MMFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR1_EL1) +#define ID_AA64MMFR1_EL1_ISS ISS_MSR_REG(ID_AA64MMFR1_EL1) #define ID_AA64MMFR1_EL1_op0 3 #define ID_AA64MMFR1_EL1_op1 0 #define ID_AA64MMFR1_EL1_CRn 0 @@ -1443,6 +1453,7 @@ /* ID_AA64MMFR2_EL1 */ #define ID_AA64MMFR2_EL1 MRS_REG(ID_AA64MMFR2_EL1) #define ID_AA64MMFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR2_EL1) +#define ID_AA64MMFR2_EL1_ISS ISS_MSR_REG(ID_AA64MMFR2_EL1) #define ID_AA64MMFR2_EL1_op0 3 #define ID_AA64MMFR2_EL1_op1 0 #define ID_AA64MMFR2_EL1_CRn 0 @@ -1545,6 +1556,7 @@ /* ID_AA64MMFR3_EL1 */ #define ID_AA64MMFR3_EL1 MRS_REG(ID_AA64MMFR3_EL1) #define ID_AA64MMFR3_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR3_EL1) +#define ID_AA64MMFR3_EL1_ISS ISS_MSR_REG(ID_AA64MMFR3_EL1) #define ID_AA64MMFR3_EL1_op0 3 #define ID_AA64MMFR3_EL1_op1 0 #define ID_AA64MMFR3_EL1_CRn 0 @@ -1632,6 +1644,7 @@ /* ID_AA64MMFR4_EL1 */ #define ID_AA64MMFR4_EL1 MRS_REG(ID_AA64MMFR4_EL1) #define ID_AA64MMFR4_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR4_EL1) +#define ID_AA64MMFR4_EL1_ISS ISS_MSR_REG(ID_AA64MMFR4_EL1) #define ID_AA64MMFR4_EL1_op0 3 #define ID_AA64MMFR4_EL1_op1 0 #define ID_AA64MMFR4_EL1_CRn 0 @@ -1641,6 +1654,7 @@ /* ID_AA64PFR0_EL1 */ #define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1) #define ID_AA64PFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR0_EL1) +#define ID_AA64PFR0_EL1_ISS ISS_MSR_REG(ID_AA64PFR0_EL1) #define ID_AA64PFR0_EL1_op0 3 #define ID_AA64PFR0_EL1_op1 0 #define ID_AA64PFR0_EL1_CRn 0 @@ -1757,6 +1771,7 @@ /* ID_AA64PFR1_EL1 */ #define ID_AA64PFR1_EL1 MRS_REG(ID_AA64PFR1_EL1) #define ID_AA64PFR1_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR1_EL1) +#define ID_AA64PFR1_EL1_ISS ISS_MSR_REG(ID_AA64PFR1_EL1) #define ID_AA64PFR1_EL1_op0 3 #define ID_AA64PFR1_EL1_op1 0 #define ID_AA64PFR1_EL1_CRn 0 @@ -1855,6 +1870,7 @@ /* ID_AA64PFR2_EL1 */ #define ID_AA64PFR2_EL1 MRS_REG(ID_AA64PFR2_EL1) #define ID_AA64PFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64PFR2_EL1) +#define ID_AA64PFR2_EL1_ISS ISS_MSR_REG(ID_AA64PFR2_EL1) #define ID_AA64PFR2_EL1_op0 3 #define ID_AA64PFR2_EL1_op1 0 #define ID_AA64PFR2_EL1_CRn 0 @@ -1864,6 +1880,7 @@ /* ID_AA64ZFR0_EL1 */ #define ID_AA64ZFR0_EL1 MRS_REG(ID_AA64ZFR0_EL1) #define ID_AA64ZFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ZFR0_EL1) +#define ID_AA64ZFR0_EL1_ISS ISS_MSR_REG(ID_AA64ZFR0_EL1) #define ID_AA64ZFR0_EL1_op0 3 #define ID_AA64ZFR0_EL1_op1 0 #define ID_AA64ZFR0_EL1_CRn 0 @@ -1929,6 +1946,7 @@ /* ID_ISAR5_EL1 */ #define ID_ISAR5_EL1 MRS_REG(ID_ISAR5_EL1) +#define ID_ISAR5_EL1_ISS ISS_MSR_REG(ID_ISAR5_EL1) #define ID_ISAR5_EL1_op0 0x3 #define ID_ISAR5_EL1_op1 0x0 #define ID_ISAR5_EL1_CRn 0x0 @@ -2065,6 +2083,7 @@ /* MVFR0_EL1 */ #define MVFR0_EL1 MRS_REG(MVFR0_EL1) +#define MVFR0_EL1_ISS ISS_MSR_REG(MVFR0_EL1) #define MVFR0_EL1_op0 0x3 #define MVFR0_EL1_op1 0x0 #define MVFR0_EL1_CRn 0x0 @@ -2124,6 +2143,7 @@ /* MVFR1_EL1 */ #define MVFR1_EL1 MRS_REG(MVFR1_EL1) +#define MVFR1_EL1_ISS ISS_MSR_REG(MVFR1_EL1) #define MVFR1_EL1_op0 0x3 #define MVFR1_EL1_op1 0x0 #define MVFR1_EL1_CRn 0x0