From owner-cvs-src@FreeBSD.ORG Tue Apr 25 05:34:18 2006 Return-Path: X-Original-To: cvs-src@freebsd.org Delivered-To: cvs-src@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id BA29616A401; Tue, 25 Apr 2006 05:34:18 +0000 (UTC) (envelope-from marck@rinet.ru) Received: from woozle.rinet.ru (woozle.rinet.ru [195.54.192.68]) by mx1.FreeBSD.org (Postfix) with ESMTP id 19FF143D48; Tue, 25 Apr 2006 05:34:17 +0000 (GMT) (envelope-from marck@rinet.ru) Received: from localhost (localhost [127.0.0.1]) by woozle.rinet.ru (8.13.6/8.13.4) with ESMTP id k3P5YGVV057814; Tue, 25 Apr 2006 09:34:16 +0400 (MSD) (envelope-from marck@rinet.ru) Date: Tue, 25 Apr 2006 09:34:16 +0400 (MSD) From: Dmitry Morozovsky To: Colin Percival In-Reply-To: <200604242117.k3OLH2RG032117@repoman.freebsd.org> Message-ID: <20060425093350.Y57625@woozle.rinet.ru> References: <200604242117.k3OLH2RG032117@repoman.freebsd.org> X-NCC-RegID: ru.rinet X-OpenPGP-Key-ID: 6B691B03 MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-2.0.2 (woozle.rinet.ru [0.0.0.0]); Tue, 25 Apr 2006 09:34:16 +0400 (MSD) Cc: cvs-src@freebsd.org, src-committers@freebsd.org, cvs-all@freebsd.org Subject: Re: cvs commit: src/sys/amd64/amd64 mp_machdep.c src/sys/i386/i386 mp_machdep.c X-BeenThere: cvs-src@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Apr 2006 05:34:18 -0000 On Mon, 24 Apr 2006, Colin Percival wrote: CP> Adjust dangerous-shared-cache-detection logic from "all shared data CP> caches are dangerous" to "a shared L1 data cache is dangerous". This CP> is a compromise between paranoia and performance: Unlike the L1 cache, CP> nobody has publicly demonstrated a cryptographic side channel which CP> exploits the L2 cache -- this is harder due to the larger size, lower CP> bandwidth, and greater associativity -- and prohibiting shared L2 CP> caches turns Intel Core Duo processors into Intel Core Solo processors. CP> CP> As before, the 'machdep.hyperthreading_allowed' sysctl will allow even CP> the L1 data cache to be shared. Any chance to MFC this to upcoming releases? Sincerely, D.Marck [DM5020, MCK-RIPE, DM3-RIPN] ------------------------------------------------------------------------ *** Dmitry Morozovsky --- D.Marck --- Wild Woozle --- marck@rinet.ru *** ------------------------------------------------------------------------