From owner-cvs-all  Tue Aug 31 20:17:30 1999
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From: Bill Paul <wpaul@FreeBSD.org>
Date: Tue, 31 Aug 1999 20:16:22 -0700 (PDT)
To: cvs-committers@FreeBSD.org, cvs-all@FreeBSD.org
Subject: cvs commit: src/sys/pci if_xl.c
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wpaul       1999/08/31 20:16:22 PDT

  Modified files:
    sys/pci              if_xl.c 
  Log:
  Just when I thought it was safe. In the original 3c905-TX NICs, the
  external NatSemi PHY chip was programmed to respond to MII address 24.
  In the 3c905B ASICs, the transceiver is internal but it's still mapped
  to MII address 24. But *some* 3Com 3c905B ASIC revisions map the
  transceiver control registers to *all* MII addresses (0 through 31).
  The miibus code probes for PHYs at all MII addresses and because of
  this unusual behavior, it will attempt to map the same PHY registers
  several times over, which doesn't work.
  
  Naturally, the 3c905B NIC that I tested happened not to exhibit this
  behavior.
  
  The fix is to tweak xl_miibus_readreg() and xl_miibus_writereg()
  to only respond when attempting to read from MII address 24. This
  is safe to do since the 3Com documentation indicates that the PHY
  and/or internal transceiver will always be mapped to address 24,
  and there are no 3Com XL NICs with more than one PHY.
  
  Revision  Changes    Path
  1.54      +15 -2     src/sys/pci/if_xl.c



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