From owner-freebsd-questions@FreeBSD.ORG Tue Jun 13 22:51:04 2006 Return-Path: X-Original-To: freebsd-questions@freebsd.org Delivered-To: freebsd-questions@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id C80DC16A41A for ; Tue, 13 Jun 2006 22:51:04 +0000 (UTC) (envelope-from bqt@update.uu.se) Received: from GW.SoftJAR.SE (205.225.216.81.static.spa.vf.siwnet.net [81.216.225.205]) by mx1.FreeBSD.org (Postfix) with ESMTP id 52C8A43D76 for ; Tue, 13 Jun 2006 22:51:00 +0000 (GMT) (envelope-from bqt@update.uu.se) Received: from [10.0.0.13] (213-65-173-246-no96.tbcn.telia.com [213.65.173.246]) by GW.SoftJAR.SE (Postfix) with ESMTP id 8D99262729; Wed, 14 Jun 2006 00:50:56 +0200 (CEST) Message-ID: <448F414D.7090302@update.uu.se> Date: Wed, 14 Jun 2006 00:50:53 +0200 From: Johnny Billquist Organization: Update Computer Club User-Agent: Mozilla Thunderbird 1.0.7 (Windows/20050923) X-Accept-Language: en-us, en MIME-Version: 1.0 To: =?ISO-8859-1?Q?Per_Fogelstr=F6m?= References: <200606131223.k5DCNkcB021980@toad.rmkhome.com> <200606131805.18778.pefo@opsycon.se> In-Reply-To: <200606131805.18778.pefo@opsycon.se> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Tue, 13 Jun 2006 22:58:43 +0000 Cc: John Nemeth , misc@openbsd.org, Otto Moerbeek , Ted Unangst , Ted Mittelstaedt , Marcus Watts , freebsd-questions@freebsd.org, =?ISO-8859-1?Q?H=E1morszky_Bal=E1zs?= , rmk@rmkhome.com, netbsd-users@netbsd.org, Nikolas Britton Subject: Re: wikipedia article X-BeenThere: freebsd-questions@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: User questions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Jun 2006 22:51:04 -0000 Per Fogelström wrote: > On Tuesday 13 June 2006 14:23, Rick Kelly wrote: > >>Johnny Billquist said: >> >>>>There's actually a cheesy way to do demand paging with microprocessors >>>>that don't support demand paging (such as the original 68000--another >>>>"16 bit" machine). The way to do this is to run two processors in >>>>parallel but skewed by one instruction. If the first one does a bad >>>>memory fetch, then the second one will not have fetched the instruction >>>>causing the fault so contains restartable machine state. Masscomp sold >>>>a machine like this once. >>> >>>Didn't the first Apollos do this? >> >>And also the Sun 1. > > > IIRC it was simpler than that. When the first cpu caused a 'miss' it was put > in wait and cpu 2 handled the pagein and then released cpu 1. Keeping the two > cpus synched, one instruction apart would have been too complicated if not > impossible... Your idea will not work, as far as I can tell. If the first CPU instruction execution causes a miss, the end result in the CPU will be pretty undefined, and you cannot restart. That's the whole point in why you'd have a second CPU shadowing the first one. So that you'd be able to restore the state as it were before the illegal memory access. And that was the problem with the original 68000. On an illegal memory reference, you would not know what state the CPU was in before the instruction, so you could not back it up, and re-execute the instruction after a page fault. Johnny -- Johnny Billquist || "I'm on a bus || on a psychedelic trip email: bqt@update.uu.se || Reading murder books pdp is alive! || tryin' to stay hip" - B. Idol