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Puga Medina" Date: Tue, 28 Feb 2017 12:21:13 +0000 (UTC) To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r435049 - in head/security/libgcrypt: . files X-SVN-Group: ports-head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-ports-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the ports tree for head List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Feb 2017 12:21:15 -0000 Author: cpm Date: Tue Feb 28 12:21:13 2017 New Revision: 435049 URL: https://svnweb.freebsd.org/changeset/ports/435049 Log: security/libgcrypt: fix build on aarch64 libtool: compile: cc -DHAVE_CONFIG_H -I. -I.. -I../src -I../src -Wa,--noexecstack -O2 -pipe -fno-strict-aliasing -std=gnu89 -MT cipher-gcm-armv8-aarch64-ce.lo -MD -MP -MF .deps/cipher-gcm-armv8-aarch64-ce.Tpo -c cipher-gcm-armv8-aarch64-ce.S -fPIC -DPIC -o .libs/cipher-gcm-armv8-aarch64-ce.o cipher-gcm-armv8-aarch64-ce.S:190:3: error: instruction requires: neon eor v31.16b, v31.16b, v31.16b ^ PR: 217271 Submitted by: krion Reported by: Simon Rozman MFH: 2017Q1 (blanket) Added: head/security/libgcrypt/files/ head/security/libgcrypt/files/extra-patch-aarch64 (contents, props changed) Modified: head/security/libgcrypt/Makefile Modified: head/security/libgcrypt/Makefile ============================================================================== --- head/security/libgcrypt/Makefile Tue Feb 28 12:06:09 2017 (r435048) +++ head/security/libgcrypt/Makefile Tue Feb 28 12:21:13 2017 (r435049) @@ -33,6 +33,10 @@ OPTIONS_DEFINE= DOCS .include +.if ${ARCH} == "armv6" || ${ARCH} == "aarch64" +EXTRA_PATCHES+= ${FILESDIR}/extra-patch-aarch64 +.endif + .if ${ARCH} == "powerpc" CONFIGURE_ARGS+= --disable-asm .endif Added: head/security/libgcrypt/files/extra-patch-aarch64 ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/security/libgcrypt/files/extra-patch-aarch64 Tue Feb 28 12:21:13 2017 (r435049) @@ -0,0 +1,68 @@ +--- cipher/cipher-gcm-armv8-aarch64-ce.S.orig 2016-11-12 10:39:35 UTC ++++ cipher/cipher-gcm-armv8-aarch64-ce.S +@@ -23,7 +23,7 @@ + defined(HAVE_COMPATIBLE_GCC_AARCH64_PLATFORM_AS) && \ + defined(HAVE_GCC_INLINE_ASM_AARCH64_CRYPTO) + +-.arch armv8-a+crypto ++.cpu generic+simd+crypto + + .text + +--- cipher/rijndael-armv8-aarch64-ce.S.orig 2017-01-18 11:28:40 UTC ++++ cipher/rijndael-armv8-aarch64-ce.S +@@ -23,7 +23,7 @@ + defined(HAVE_COMPATIBLE_GCC_AARCH64_PLATFORM_AS) && \ + defined(HAVE_GCC_INLINE_ASM_AARCH64_CRYPTO) + +-.arch armv8-a+crypto ++.cpu generic+simd+crypto + + .text + +--- cipher/sha1-armv8-aarch64-ce.S.orig 2016-11-12 10:39:35 UTC ++++ cipher/sha1-armv8-aarch64-ce.S +@@ -23,7 +23,7 @@ + defined(HAVE_COMPATIBLE_GCC_AARCH64_PLATFORM_AS) && \ + defined(HAVE_GCC_INLINE_ASM_AARCH64_CRYPTO) && defined(USE_SHA1) + +-.arch armv8-a+crypto ++.cpu generic+simd+crypto + + .text + +--- cipher/sha256-armv8-aarch64-ce.S.orig 2016-11-12 10:39:35 UTC ++++ cipher/sha256-armv8-aarch64-ce.S +@@ -23,7 +23,7 @@ + defined(HAVE_COMPATIBLE_GCC_AARCH64_PLATFORM_AS) && \ + defined(HAVE_GCC_INLINE_ASM_AARCH64_CRYPTO) && defined(USE_SHA256) + +-.arch armv8-a+crypto ++.cpu generic+simd+crypto + + .text + +--- configure.ac.orig 2017-01-18 11:37:00 UTC ++++ configure.ac +@@ -1623,7 +1623,7 @@ AC_CACHE_CHECK([whether GCC inline assem + gcry_cv_gcc_inline_asm_aarch64_neon=no + AC_COMPILE_IFELSE([AC_LANG_SOURCE( + [[__asm__( +- ".arch armv8-a\n\t" ++ ".cpu generic+simd\n\t" + "mov w0, \#42;\n\t" + "dup v0.8b, w0;\n\t" + "ld4 {v0.8b,v1.8b,v2.8b,v3.8b},[x0],\#32;\n\t" +@@ -1648,7 +1648,11 @@ AC_CACHE_CHECK([whether GCC inline assem + gcry_cv_gcc_inline_asm_aarch64_crypto=no + AC_COMPILE_IFELSE([AC_LANG_SOURCE( + [[__asm__( +- ".arch armv8-a+crypto\n\t" ++ ".cpu generic+simd\n\t" ++ ++ "mov w0, \#42;\n\t" ++ "dup v0.8b, w0;\n\t" ++ "ld4 {v0.8b,v1.8b,v2.8b,v3.8b},[x0],\#32;\n\t" + + "sha1h s0, s0;\n\t" + "sha1c q0, s0, v0.4s;\n\t"