From owner-freebsd-amd64@FreeBSD.ORG Tue Apr 4 12:47:21 2006 Return-Path: X-Original-To: freebsd-amd64@freebsd.org Delivered-To: freebsd-amd64@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 65ADA16A401 for ; Tue, 4 Apr 2006 12:47:21 +0000 (UTC) (envelope-from andrew@areilly.bpa.nu) Received: from omta01ps.mx.bigpond.com (omta01ps.mx.bigpond.com [144.140.82.153]) by mx1.FreeBSD.org (Postfix) with ESMTP id BFC6E43D75 for ; Tue, 4 Apr 2006 12:47:07 +0000 (GMT) (envelope-from andrew@areilly.bpa.nu) Received: from areilly.bpa.nu ([141.168.4.160]) by omta01ps.mx.bigpond.com with ESMTP id <20060404124706.QEEJ19070.omta01ps.mx.bigpond.com@areilly.bpa.nu> for ; Tue, 4 Apr 2006 12:47:06 +0000 Received: (qmail 37966 invoked by uid 501); 4 Apr 2006 12:48:45 -0000 Date: Tue, 4 Apr 2006 22:48:45 +1000 From: Andrew Reilly To: Scott Long Message-ID: <20060404124845.GA37816@gurney.reilly.home> References: <44301C6D.3010206@rogers.com> <200604031442.43477.jhb@freebsd.org> <44318E3F.6080808@rogers.com> <20060403211943.GA99241@troutmask.apl.washington.edu> <44319240.8070203@samsco.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <44319240.8070203@samsco.org> User-Agent: Mutt/1.4.2.1i Cc: freebsd-amd64@freebsd.org Subject: Re: Status of NX bit support. X-BeenThere: freebsd-amd64@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the AMD64 platform List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Apr 2006 12:47:21 -0000 On Mon, Apr 03, 2006 at 03:23:12PM -0600, Scott Long wrote: > Steve Kargl wrote: > >You're joking, right? How many registers are available for the > >i386? How many registers are available to an AMD64 cpu in > >64-bit mode? > > You also get less efficient cache utilization due to the wider data > types that are in use. It seems to be mostly a wash between the > advantages of more registers and the cost of lower cache efficiency. > amd64 is nice when you need more kernel address space and/or more > process address space. I know I'm probably being barking mad, here, but what I'd really like for my AMD64 workstation system is to be able to run it in AMD64-mode, but with 32-bit pointers. I vaguely remember reading some early AMD bumpf that that could be a supported configuration, somehow. Seems like it should just be a compiler switch, to specify 32-bit loads and stores for pointer values, and probably some checking in the pmap system to make sure that nothing is mapped outside the 32-bit range... Anyone know if it's been done? How it performs, if it's been done? I do a fair bit of DSP simulation work, and 64-bit long-longs are very handy to have go fast, and more registers and register-based calling conventions are always a good thing. I have no need for 64-bit addresses, at least at the process level, and I suspect that most workstation users would be in much the same boat... Didn't MIPS, Sun and Apple support such an arrangement on R4000+, SPARCv?8 and PowerPC970 (G5) systems? Cheers, -- Andrew