From owner-freebsd-current@FreeBSD.ORG Fri Sep 21 19:48:48 2007 Return-Path: Delivered-To: freebsd-current@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id C706616A469; Fri, 21 Sep 2007 19:48:48 +0000 (UTC) (envelope-from cswiger@mac.com) Received: from mail-out3.apple.com (mail-out3.apple.com [17.254.13.22]) by mx1.freebsd.org (Postfix) with ESMTP id 9E38C13C4A5; Fri, 21 Sep 2007 19:48:48 +0000 (UTC) (envelope-from cswiger@mac.com) Received: from relay13.apple.com (relay13.apple.com [17.128.113.29]) by mail-out3.apple.com (Postfix) with ESMTP id 7BA8B11F1DB9; Fri, 21 Sep 2007 12:48:48 -0700 (PDT) Received: from relay13.apple.com (unknown [127.0.0.1]) by relay13.apple.com (Symantec Mail Security) with ESMTP id 5683B2805B; Fri, 21 Sep 2007 12:48:48 -0700 (PDT) X-AuditID: 1180711d-a235dbb000006cd8-6d-46f4201fe1d2 Received: from [17.214.13.96] (cswiger1.apple.com [17.214.13.96]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by relay13.apple.com (Apple SCV relay) with ESMTP id D06FC28097; Fri, 21 Sep 2007 12:48:47 -0700 (PDT) In-Reply-To: <20070921193340.GA70365@eos.sc1.parodius.com> References: <200709132302.l8DN2Tv5076033@repoman.freebsd.org> <46E9FC0C.70607@FreeBSD.org> <46F1A96F.2040602@FreeBSD.org> <20070921193340.GA70365@eos.sc1.parodius.com> Mime-Version: 1.0 (Apple Message framework v752.2) Content-Type: text/plain; charset=US-ASCII; delsp=yes; format=flowed Message-Id: <386DE04B-11B1-47A9-BF12-73D770C6A851@mac.com> Content-Transfer-Encoding: 7bit From: Chuck Swiger Date: Fri, 21 Sep 2007 12:48:46 -0700 To: Jeremy Chadwick X-Mailer: Apple Mail (2.752.2) X-Brightmail-Tracker: AAAAAA== Cc: Rui Paulo , Doug Barton , "Constantine A. Murenin" , Shteryana Shopova , FreeBSD Current , Alexander Leidinger Subject: Re: GSoC2007: cnst-sensors.2007-09-13.patch X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Sep 2007 19:48:48 -0000 On Sep 21, 2007, at 12:33 PM, Jeremy Chadwick wrote: > On Fri, Sep 21, 2007 at 12:20:07PM -0700, Chuck Swiger wrote: >> The CPU itself has a thermal control circuit which puts the CPU >> into a >> reduced duty cycle (ie, it reduces the core voltage and stops the >> CPU for >> something like 10 clocks, and then allows one clock through) and >> continues >> to run the CPU at about 10% of normal workload until the >> temperature falls >> below the critical threshold. There's a good document here: > > Are you referring to the Core 2 Duo C1E (Enhanced Halt State) > processor > feature or the EIST feature? I'm guessing C1E. Note that for C1E to > work, it has to be enabled/available in the BIOS. > > I'll add that C1E is really great, dropping temperatures during idle > periods by about 5-6C from what I've seen. The additional C[234]E > states (at least for desktops) don't provide much benefit, but C1E > definitely does. Nope, although the second link I mentioned does discuss the state diagram the Core processors use for transitioning between various ACPI sleep states also in order to reduce power usage and hence thermal dissipation. That does indeed require ACPI to be enabled/ supported in the BIOS, as you've said. Anyway, the PROCHOT signal originated back circa the Pentium-3's or Pentium-M/Centrino's and has been included with the P4/Xeon and now Core/Core2's also-- it's a fallback mechanism which does not require BIOS support, and involves changes which reduce the CPU core voltage supplied by the voltage regulator circuitry and what Intel calls "modulating" the CPU clock to reduce the effective clock frequency it is running at by running at roughly a 10% duty cycle (this varies depending on the specific part), even if the external clock doesn't change the way it does with SpeedStep/EIST. -- -Chuck