From owner-p4-projects@FreeBSD.ORG Tue Feb 26 15:19:51 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 49125106568E; Tue, 26 Feb 2008 15:19:51 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 0447A106567F for ; Tue, 26 Feb 2008 15:19:51 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 08C6A13C45E for ; Tue, 26 Feb 2008 15:19:50 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m1QFJnX7049801 for ; Tue, 26 Feb 2008 15:19:49 GMT (envelope-from rrs@cisco.com) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m1QFJngv049798 for perforce@freebsd.org; Tue, 26 Feb 2008 15:19:49 GMT (envelope-from rrs@cisco.com) Date: Tue, 26 Feb 2008 15:19:49 GMT Message-Id: <200802261519.m1QFJngv049798@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to rrs@cisco.com using -f From: "Randall R. Stewart" To: Perforce Change Reviews Cc: Subject: PERFORCE change 136258 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Feb 2008 15:19:51 -0000 http://perforce.freebsd.org/chv.cgi?CH=136258 Change 136258 by rrs@rrs-mips2-jnpr on 2008/02/26 15:19:26 Lops off the status. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/psraccess.S#5 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/psraccess.S#5 (text+ko) ==== @@ -133,7 +133,7 @@ #ifdef TARGET_OCTEON .set mips64 .word 0x041626000 #di v0 - + and v0, SR_INT_ENAB # return old interrupt enable bit #if defined(ISA_MIPS32) .set mips32 #elif defined(ISA_MIPS64) @@ -143,6 +143,7 @@ #endif #else mfc0 v0, COP_0_STATUS_REG # read status register + and v0, v0, SR_INT_ENAB nop and v1, v0, ~SR_INT_ENAB mtc0 v1, COP_0_STATUS_REG # disable all interrupts @@ -157,6 +158,7 @@ #ifdef TARGET_OCTEON .set mips64 .word 0x041626020 #ei v0 + and v0, SR_INT_ENAB # return old interrupt enable bit #if defined(ISA_MIPS32) .set mips32 #elif defined(ISA_MIPS64)