From owner-svn-src-head@freebsd.org Fri Jan 27 19:47:56 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id C32FBCC4622; Fri, 27 Jan 2017 19:47:56 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from mail.baldwin.cx (bigwig.baldwin.cx [IPv6:2001:470:1f11:75::1]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id A3927FDD; Fri, 27 Jan 2017 19:47:56 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from ralph.baldwin.cx (c-73-231-226-104.hsd1.ca.comcast.net [73.231.226.104]) by mail.baldwin.cx (Postfix) with ESMTPSA id A097710A7B9; Fri, 27 Jan 2017 14:47:55 -0500 (EST) From: John Baldwin To: Sean Bruno Cc: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: Re: svn commit: r312755 - head/sys/net Date: Fri, 27 Jan 2017 11:28:23 -0800 Message-ID: <6817684.C985jk9qCN@ralph.baldwin.cx> User-Agent: KMail/4.14.10 (FreeBSD/11.0-STABLE; KDE/4.14.10; amd64; ; ) In-Reply-To: <201701251437.v0PEb5D7047773@repo.freebsd.org> References: <201701251437.v0PEb5D7047773@repo.freebsd.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.4.3 (mail.baldwin.cx); Fri, 27 Jan 2017 14:47:55 -0500 (EST) X-Virus-Scanned: clamav-milter 0.99.2 at mail.baldwin.cx X-Virus-Status: Clean X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jan 2017 19:47:56 -0000 On Wednesday, January 25, 2017 02:37:05 PM Sean Bruno wrote: > Author: sbruno > Date: Wed Jan 25 14:37:05 2017 > New Revision: 312755 > URL: https://svnweb.freebsd.org/changeset/base/312755 > > Log: > Add error checking to the pci_find_cap(, PCIY_MSIX,) call that is returns > success and a good value. Only then try to use it and set the MSIX_ENABLE > bit. > > With the current em(4) driver we have observed failures in this case in a > specific environment when pci_find_cap() would not return the assumed > value, which meant we ended up writing to PCI register 2 (PCI_DEVICE_ID) > which is read-only. Why is this writing directly to the MSIX registers at all? pci_alloc_msix() etc. handle those registers for all other drivers and proper suspend/resume depends on drivers using the existing PCI API for managing MSI and MSI-X. > Modified: head/sys/net/iflib.c > ============================================================================== > --- head/sys/net/iflib.c Wed Jan 25 13:42:38 2017 (r312754) > +++ head/sys/net/iflib.c Wed Jan 25 14:37:05 2017 (r312755) > @@ -4779,15 +4783,20 @@ iflib_msix_init(if_ctx_t ctx) > uint16_t pci_cmd_word; > int msix_ctrl, rid; > > - rid = 0; > pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); > pci_cmd_word |= PCIM_CMD_BUSMASTEREN; > pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2); This should use 'pci_enable_busmaster()' like other drivers rather than manipulating registers directly. -- John Baldwin