From nobody Fri Feb 20 10:13:25 2026 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4fHR0P5HNpz6SZ7G for ; Fri, 20 Feb 2026 10:13:25 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R12" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4fHR0P3rrMz442N for ; Fri, 20 Feb 2026 10:13:25 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1771582405; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=aXRNRWzD5v08WFhnGddPgxhEV0APEwJKDfRvOFfGvSw=; b=A9cPk8dnkwNP1r3YXBzECFqtk3zEiCz6p4X1fzNnFH6B5PB07d20YoZ0ICGqdKP6YaWRMN L1T+O3rT0vnbRn/20by/3xRhbCK6LyaSjXGrxGhXUeLQokbluJ2h5nIdOfkAqk8GpFCJjA FyiRFrCW12MtyUcy13B8CHVwHpNkQe3/ZAwWUkzlUNSy9jY8KgpbgDTuzHpwYoGe7SMK/4 BvtrX/k5wNVg6PW/AbMOFP7UUJyKwI2JUKTEZKt+XSIskJjOhW19C18CFUALhnosSsoKN/ gK40c+0o+cA1DKS8ws6aA7SmD50m39XNs0erNo1SGkB7t7QQ8Jvzp44GJgUQpQ== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1771582405; a=rsa-sha256; cv=none; b=EaDNdhSqqkVgBqTZzvwBm852zIGXFzg9FIVcvF4HSvkkDgBUcawvAhzoX85KhzqG38h3GE Rln0SI0hCSfwB7Se3FK8sYBD/9mdTGPgTVcHlyq50SU5/eByLDIlEbb5U8a2d3i3hCv/lS 6nFPYgfdkNorMddh2CBgW02X5NAwrpAx7gLmMnpMaaGLYdifr++ElervhptnmWXgJ0jS9V niduS4cmiSH+HN9o58zNtI2GADysWYiOs9GbrK8OyIbZqLhrQB/F+xeR5tkdagsXxqjGlX tGxwXg22+t22WJBHWk3H9nkYi2jfOInS83ubgrd7jH0prxUzOpBCyF4cI/KlTA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1771582405; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=aXRNRWzD5v08WFhnGddPgxhEV0APEwJKDfRvOFfGvSw=; b=GUYVhM0lHmQYHthWernn0GVkR55T0prBO5gWHhfRwXfew8MWLzfdubktlYsQgf0CLYoSrB mDEQABmMpnzWmgjDlrx1YcFss31kaZ7RUxB3ofJLn5jNPgWLuhlrjlojX7EvSQbsyhy07s ruLAVlJXPAa5Zt9u3D4lAQhWNJfuwz1v1V3wEGvWsNNk3KIACewHuD0Pffr6cuCMuSjMO9 urzvlNHCfmj3kk0j4Bu9cif26afooCWMOw/vTlnBRxYg6KfvlwjyVAC11N0Pz6gonDHh9O fYidBTtg5pwFuqqIW0dGlh+St7LHWfBqJyJhgpIQNIUL1funBQyJLE93ZgXBVA== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4fHR0P36J3z7r0 for ; Fri, 20 Feb 2026 10:13:25 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 23ae6 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Fri, 20 Feb 2026 10:13:25 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Olivier Certner Subject: git: b69a396de211 - main - hwpstate_amd(4): CPPC: Allow attaching even if CAPABILITY_1 cannot be read List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: olce X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: b69a396de211feb1dcfe6a7e95d1b23ae53f916a Auto-Submitted: auto-generated Date: Fri, 20 Feb 2026 10:13:25 +0000 Message-Id: <699833c5.23ae6.70f7062d@gitrepo.freebsd.org> The branch main has been updated by olce: URL: https://cgit.FreeBSD.org/src/commit/?id=b69a396de211feb1dcfe6a7e95d1b23ae53f916a commit b69a396de211feb1dcfe6a7e95d1b23ae53f916a Author: Olivier Certner AuthorDate: 2026-02-09 17:19:51 +0000 Commit: Olivier Certner CommitDate: 2026-02-20 10:12:53 +0000 hwpstate_amd(4): CPPC: Allow attaching even if CAPABILITY_1 cannot be read If that MSR cannot be read, we fallback to defaults specified by the ACPI specification, as we are already doing when the minimum and maximum values in there look bogus. Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D55252 --- sys/x86/cpufreq/hwpstate_amd.c | 45 ++++++++++++++++++++++++++---------------- 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/sys/x86/cpufreq/hwpstate_amd.c b/sys/x86/cpufreq/hwpstate_amd.c index bbb8f5b864f8..72fe6dbf6014 100644 --- a/sys/x86/cpufreq/hwpstate_amd.c +++ b/sys/x86/cpufreq/hwpstate_amd.c @@ -772,7 +772,10 @@ enable_cppc_cb(void *args) uint64_t lowest_perf, highest_perf; int error; - /* We proceed sequentially, so we'll clear out errors on progress. */ + /* + * We proceed mostly sequentially, so we'll clear out errors on + * progress. + */ data->res = HWP_ERROR_CPPC_ENABLE | HWP_ERROR_CPPC_CAPS | HWP_ERROR_CPPC_REQUEST | HWP_ERROR_CPPC_REQUEST_WRITE; @@ -784,9 +787,9 @@ enable_cppc_cb(void *args) data->res &= ~HWP_ERROR_CPPC_ENABLE; error = rdmsr_safe(MSR_AMD_CPPC_CAPS_1, &data->caps); - if (error != 0) - return; - data->res &= ~HWP_ERROR_CPPC_CAPS; + /* We can do away without CAPABILITY_1, so just continue on error. */ + if (error == 0) + data->res &= ~HWP_ERROR_CPPC_CAPS; error = get_cppc_request(sc); if (error != 0) @@ -804,20 +807,28 @@ enable_cppc_cb(void *args) /* Enable autonomous mode by setting desired performance to 0. */ SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_DES_PERF_BITS, 0); /* - * When MSR_AMD_CPPC_CAPS_1 stays at its reset value (0) before CPPC - * activation (not supposed to happen, but happens in the field), we use - * reasonable default values that are explicitly described by the ACPI - * spec (all 0s for the minimum value, all 1s for the maximum one). - * Going further, we actually do the same as long as the minimum and - * maximum performance levels are not sorted or are equal (in which case - * CPPC is not supposed to make sense at all), which covers the reset - * value case. + * Assuming reading MSR_AMD_CPPC_CAPS_1 succeeded, if it stays at its + * reset value (0) before CPPC activation (not supposed to happen, but + * happens in the field), we use reasonable default values that are + * explicitly described by the ACPI spec (all 0s for the minimum value, + * all 1s for the maximum one). Going further, we actually do the same + * as long as the minimum and maximum performance levels are not sorted + * or are equal (in which case CPPC is not supposed to make sense at + * all), which covers the reset value case. And we also fallback to + * these if MSR_AMD_CPPC_CAPS_1 could not be read at all. */ - lowest_perf = BITS_VALUE(AMD_CPPC_CAPS_1_LOWEST_PERF_BITS, data->caps); - highest_perf = BITS_VALUE(AMD_CPPC_CAPS_1_HIGHEST_PERF_BITS, data->caps); - if (lowest_perf >= highest_perf) { - lowest_perf = 0; - highest_perf = -1; + lowest_perf = 0; + highest_perf = -1; + if (!hwp_has_error(data->res, HWP_ERROR_CPPC_CAPS)) { + const uint64_t lowest_cand = + BITS_VALUE(AMD_CPPC_CAPS_1_LOWEST_PERF_BITS, data->caps); + const uint64_t highest_cand = + BITS_VALUE(AMD_CPPC_CAPS_1_HIGHEST_PERF_BITS, data->caps); + + if (lowest_cand < highest_cand) { + lowest_perf = lowest_cand; + highest_perf = highest_cand; + } } SET_BITS_VALUE(data->request, AMD_CPPC_REQUEST_MIN_PERF_BITS, lowest_perf);