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Date: Wed, 16 Jun 2004 11:23:13 +0100
From: Bruce M Simpson <bms@spc.org>
To: Martin Nilsson <martin@gneto.com>,
	Alexander Leidinger <Alexander@Leidinger.net>, current@freebsd.org
Message-ID: <20040616102313.GT32244@empiric.dek.spc.org>
References: <20040616112758.46677e25@Magellan.Leidinger.net>
	<40D016F2.2080904@gneto.com> <20040616101102.GQ32244@empiric.dek.spc.org>
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Subject: Re: How to determine the L2 cache size on non-AMD CPUs (automatic
	page queue color tuning)?
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On Wed, Jun 16, 2004 at 11:11:02AM +0100, Bruce M Simpson wrote:
> On Wed, Jun 16, 2004 at 11:46:26AM +0200, Martin Nilsson wrote:
> > 
> > How much effct on performance does a wrong cache size value have?
> 
> Gag. I posted something on this whole subject last *year*, and still
> haven't gotten round to code.

http://www.usenix.org/publications/library/proceedings/als00/2000papers/papers/full_papers/sears/sears_html/

is a good starting point.

The points Dillon made this time last year on -hackers/in private mail
about mutex alignment on cache line boundaries also apply...

BMS