Date: Fri, 28 Apr 2000 19:26:53 -0700 (PDT) From: Matthew Dillon <dillon@apollo.backplane.com> To: Terry Lambert <tlambert@primenet.com> Cc: tlambert@primenet.com (Terry Lambert), jgowdy@home.com (Jeremiah Gowdy), smp@csn.net (Steve Passe), jim@thehousleys.net (James Housley), freebsd-smp@FreeBSD.ORG Subject: Re: hlt instructions and temperature issues Message-ID: <200004290226.TAA20985@apollo.backplane.com> References: <200004290120.SAA11745@usr08.primenet.com>
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Terry, MESI caching is the *problem* here, not the thing that makes
the issue go away.
Having multiple cpu's XORing to the same memory location, whether or not
they are only messing with their own bits, MUST be a locked instruction
outside the BGL or you *will* get data corruption. Intel does not
use cache-coherent read-modify-write instructions without the lock
prefix, except for a special case in one of the cmpexg instructions.
And we are outside the BGL at this point in the scheduler code.
It is precisely attempting to do something like that which will cause
the MESI caching to go haywire. XOR latency on an 8-cpu box with
all cpu's trying to mess with the bits will border on 1.6 uS. We are
talking about creating hundreds of cycles of overhead in the scheduling
code for no good reason here.
-Matt
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