From owner-freebsd-questions  Wed Nov  3 16:20:24 1999
Delivered-To: freebsd-questions@freebsd.org
Received: from dorifer.heim3.tu-clausthal.de (dorifer.heim3.tu-clausthal.de [139.174.243.252])
	by hub.freebsd.org (Postfix) with ESMTP id 93B3C1506A
	for <freebsd-questions@FreeBSD.ORG>; Wed,  3 Nov 1999 16:20:02 -0800 (PST)
	(envelope-from olli@dorifer.heim3.tu-clausthal.de)
Received: (from olli@localhost)
	by dorifer.heim3.tu-clausthal.de (8.8.8/8.8.8) id BAA06030
	for freebsd-questions@FreeBSD.ORG; Thu, 4 Nov 1999 01:18:34 +0100 (CET)
	(envelope-from olli)
Date: Thu, 4 Nov 1999 01:18:34 +0100 (CET)
From: Oliver Fromme <olli@dorifer.heim3.tu-clausthal.de>
Message-Id: <199911040018.BAA06030@dorifer.heim3.tu-clausthal.de>
To: freebsd-questions@FreeBSD.ORG
Subject: Re: Athlons..
Organization: Administration Heim 3
Reply-To: freebsd-questions@FreeBSD.ORG
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 8bit
X-Newsreader: TIN [version 1.2 RZTUC(3) PL2]
Sender: owner-freebsd-questions@FreeBSD.ORG
Precedence: bulk
X-Loop: FreeBSD.ORG

Mark Ovens wrote in list.freebsd-questions:
 > On Tue, Nov 02, 1999 at 02:28:40AM +0100, Oliver Fromme wrote:
 > > Stephen Roome wrote in list.freebsd-questions:
 > >  > Does anyone know if the following example, taken from AMD's documentation,
 > >  > would improve bcopy performance on the Athlon? (over the routine that would be
 > >  > defaulted to ?)
 > > 
 > > This _might_ improve performance when copying very large
 > > regions.  However, the problem is, that movq (which is an
 > > MMX instruction) clobbers the FPU registers, which is a
 > > bad thing.
 > 
 > ISTR reading that this is an Intel-only problem and that AMD's
 > 3D-Now! instructions don't clobber the FPU registers. Can't remember
 > the reason though, dedicated registers?

Unfortunately, that is not true.  The 3DNow instructions use
exactly the same registers as the MMX instructions.  In fact,
you can use MMX and 3DNow computations at the same time.  For
example, you can use an MMX instruction to negate the result of
a 3DNow computation efficiently.

There are two things which make 3DNow CPUs somewhat more usable
than MMX-only CPUs:  First, 3DNow supports floating point
operations (MMX is integer only), so you usually don't have to
switch between standard FPU mode and 3DNow (or at least not
that often).  Second, AMD invented a new instruction called
"femms" which can be used to switch between FPU and 3DNow
instructions, much faster than the intel MMX CPUs can.

But, still, any such switch will clear FPU and 3DNow/MMX
registers, because theyre mapped to the same register space
internally.  Otherwise, it would not be possible to have
multiple programs working with MMX/3DNow in a multitasking
operating system in which the scheduler has no specific
support for saving and restoring MMX/3DNow registers.

Regards
   Oliver

PS:  I programmed both MMX and 3DNow stuff in assembler under
FreeBSD (e.g. an improved version of the Seti@home client), so
I think I know it pretty well.  ;-)

-- 
Oliver Fromme, Leibnizstr. 18/61, 38678 Clausthal, Germany
(Info: finger userinfo:olli@dorifer.heim3.tu-clausthal.de)

"In jedem Stück Kohle wartet ein Diamant auf seine Geburt"
                                         (Terry Pratchett)


To Unsubscribe: send mail to majordomo@FreeBSD.org
with "unsubscribe freebsd-questions" in the body of the message