Date: Wed, 23 Sep 2020 03:12:58 +0000 (UTC) From: Brandon Bergren <bdragon@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r366061 - head/share/man/man7 Message-ID: <202009230312.08N3CwUm035379@repo.freebsd.org>
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Author: bdragon Date: Wed Sep 23 03:12:58 2020 New Revision: 366061 URL: https://svnweb.freebsd.org/changeset/base/366061 Log: arch(7): PowerPC64LE architecture definition Document the new powerpc64le arch's initial specifications. Certain things are subject to change while this is experimental. The most likely change is that long double may switch to quad, dependent on POWER8 emulation assistance for __float128 being set up in the compiler (as POWER8 does not have IEEE-compatible 128-bit hardware float, unlike POWER9.) Sponsored by: Tag1 Consulting, Inc. Modified: head/share/man/man7/arch.7 Modified: head/share/man/man7/arch.7 ============================================================================== --- head/share/man/man7/arch.7 Wed Sep 23 03:02:45 2020 (r366060) +++ head/share/man/man7/arch.7 Wed Sep 23 03:12:58 2020 (r366061) @@ -26,7 +26,7 @@ .\" .\" $FreeBSD$ .\" -.Dd June 23, 2020 +.Dd September 22, 2020 .Dt ARCH 7 .Os .Sh NAME @@ -110,6 +110,7 @@ architectures, the final release. .It powerpc Ta 6.0 .It powerpcspe Ta 12.0 .It powerpc64 Ta 6.0 +.It powerpc64le Ta 13.0 .It riscv64 Ta 12.0 .It riscv64sf Ta 12.0 .It sparc64 Ta 5.0 Ta 12.x @@ -206,6 +207,7 @@ Machine-dependent type sizes: .It powerpc Ta 4 Ta 8 Ta 8 .It powerpcspe Ta 4 Ta 8 Ta 8 .It powerpc64 Ta 8 Ta 8 Ta 8 +.It powerpc64le Ta 8 Ta 8 Ta 8 .It riscv64 Ta 8 Ta 16 Ta 8 .It riscv64sf Ta 8 Ta 16 Ta 8 .El @@ -232,6 +234,7 @@ is 8 bytes on all supported architectures except i386. .It powerpc Ta big Ta unsigned .It powerpcspe Ta big Ta unsigned .It powerpc64 Ta big Ta unsigned +.It powerpc64le Ta little Ta unsigned .It riscv64 Ta little Ta signed .It riscv64sf Ta little Ta signed .El @@ -255,6 +258,7 @@ is 8 bytes on all supported architectures except i386. .It powerpc Ta 4K .It powerpcspe Ta 4K .It powerpc64 Ta 4K +.It powerpc64le Ta 4K .It riscv64 Ta 4K, 2M, 1G .It riscv64sf Ta 4K, 2M, 1G .El @@ -278,6 +282,7 @@ is 8 bytes on all supported architectures except i386. .It powerpc Ta hard Ta hard, double precision .It powerpcspe Ta hard Ta hard, double precision .It powerpc64 Ta hard Ta hard, double precision +.It powerpc64le Ta hard Ta hard, double precision .It riscv64 Ta hard Ta hard, quad precision .It riscv64sf Ta soft Ta soft, quad precision .El @@ -311,7 +316,7 @@ or similar things like boot sequences. .It arm Ta arm Ta armv6, armv7 .It i386 Ta i386 Ta i386 .It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32 -.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64 +.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64, powerpc64le .It riscv Ta riscv Ta riscv64, riscv64sf .El .Ss Predefined Macros @@ -356,6 +361,7 @@ Architecture-specific macros: .It powerpc Ta Dv __powerpc__ .It powerpcspe Ta Dv __powerpc__ , Dv __SPE__ .It powerpc64 Ta Dv __powerpc__ , Dv __powerpc64__ +.It powerpc64le Ta Dv __powerpc__ , Dv __powerpc64__ .It riscv64 Ta Dv __riscv , Dv __riscv_xlen == 64 .It riscv64sf Ta Dv __riscv , Dv __riscv_xlen == 64 , Dv __riscv_float_abi_soft .El
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