Date: Sat, 21 Aug 2004 08:10:19 GMT From: Eric Anholt <eta@lclark.edu> To: freebsd-i386@FreeBSD.org Subject: Re: i386/59854 Message-ID: <200408210810.i7L8AJQj071742@freefall.freebsd.org>
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The following reply was made to PR i386/59854; it has been noted by GNATS. From: Eric Anholt <eta@lclark.edu> To: gnats <freebsd-gnats-submit@FreeBSD.ORG> Cc: green@FreeBSD.org Subject: Re: i386/59854 Date: Sat, 21 Aug 2004 01:02:02 -0700 --=-jFP6IGiskqaP/oBwf8Wv Content-Type: text/plain Content-Transfer-Encoding: 7bit Attached is a patch that may help with AMD AGP issues. It was improperly handling aperture sizes of 512M or higher, and the shutdown function (called as part of rebooting) may have been broken enough to confuse the hardware. If people could give it a try and tell me if it improves the situation at all, that would be great. I'm still doubtful it'll fix this PR, but it's a step. -- Eric Anholt eta@lclark.edu http://people.freebsd.org/~anholt/ anholt@FreeBSD.org --=-jFP6IGiskqaP/oBwf8Wv Content-Disposition: attachment; filename=agp-amd.diff Content-Type: text/x-patch; name=agp-amd.diff; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Index: agp_amd.c =================================================================== RCS file: /home/ncvs/src/sys/pci/agp_amd.c,v retrieving revision 1.21 diff -u -u -r1.21 agp_amd.c --- agp_amd.c 16 Aug 2004 12:23:53 -0000 1.21 +++ agp_amd.c 21 Aug 2004 07:48:31 -0000 @@ -269,6 +269,12 @@ /* Enable the TLB and flush */ WRITE2(AGP_AMD751_STATUS, READ2(AGP_AMD751_STATUS) | AGP_AMD751_STATUS_GCE); + + /* Setting bit 0 is required for the size to be valid. */ + pci_write_config(dev, + AGP_AMD751_APCTRL, + pci_read_config(dev, AGP_AMD751_APCTRL, 1) | 1, 1); + AGP_FLUSH_TLB(dev); return 0; @@ -313,7 +319,7 @@ /* * The aperture size is equal to 32M<<vas. */ - vas = (pci_read_config(dev, AGP_AMD751_APCTRL, 1) & 0x06) >> 1; + vas = (pci_read_config(dev, AGP_AMD751_APCTRL, 1) & 0x0e) >> 1; return (32*1024*1024) << vas; } @@ -321,6 +327,7 @@ agp_amd_set_aperture(device_t dev, u_int32_t aperture) { int vas; + u_int32_t apctrl; /* * Check for a power of two and make sure its within the @@ -331,15 +338,15 @@ || aperture > 2U*1024*1024*1024) return EINVAL; - vas = ffs(aperture / 32*1024*1024) - 1; + vas = ffs(aperture / (32*1024*1024)) - 1; /* * While the size register is bits 1-3 of APCTRL, bit 0 must be * set for the size value to be 'valid' */ + apctrl = pci_read_config(dev, AGP_AMD751_APCTRL, 1); pci_write_config(dev, AGP_AMD751_APCTRL, - (((pci_read_config(dev, AGP_AMD751_APCTRL, 1) & ~0x06) - | ((vas << 1) | 1))), 1); + (apctrl & ~0x0e) | (vas << 1) | 1, 1); return 0; } --=-jFP6IGiskqaP/oBwf8Wv--
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