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From: Zbigniew Bodek <zbb@FreeBSD.org>
Date: Fri, 17 Jul 2015 14:33:48 +0000 (UTC)
To: src-committers@freebsd.org, svn-src-all@freebsd.org,
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Subject: svn commit: r285655 - head/sys/arm64/arm64
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Author: zbb
Date: Fri Jul 17 14:33:47 2015
New Revision: 285655
URL: https://svnweb.freebsd.org/changeset/base/285655

Log:
  Fix possible coherency issues between PEs related to I-cache
  
  Basing on B.2.3.4:
  Synchronization and coherency issues between data and
  instruction accesses.
  
  To ensure that modified instructions are visible to all PEs
  (Processing Elements) in a shareability domain one need to
  perform following sequence:
      1. Clean D-cache
      2. Ensure the visibility of data cleaned from cache
      3. Invalidate I-cache
      4. Ensure completion
      5. In SMP system PE must issue isb to ensure execution of the
         modified instructions
  
  Reviewed by:   andrew
  Obtained from: Semihalf
  Sponsored by:  The FreeBSD Foundation
  Differential Revision: https://reviews.freebsd.org/D3106

Modified:
  head/sys/arm64/arm64/cpufunc_asm.S

Modified: head/sys/arm64/arm64/cpufunc_asm.S
==============================================================================
--- head/sys/arm64/arm64/cpufunc_asm.S	Fri Jul 17 14:08:08 2015	(r285654)
+++ head/sys/arm64/arm64/cpufunc_asm.S	Fri Jul 17 14:33:47 2015	(r285655)
@@ -61,17 +61,18 @@ __FBSDID("$FreeBSD$");
 	add	x1, x1, x2		/* Add these to the size */
 	bic	x0, x0, x4		/* Clear the low bit of the address */
 1:
+	dc	\dcop, x0
+	dsb	ish
 .if \ic != 0
 	ic	\icop, x0
+	dsb	ish
 .endif
-	dc	\dcop, x0
 	add	x0, x0, x3		/* Move to the next line */
 	subs	x1, x1, x3		/* Reduce the size */
 	b.hi	1b			/* Check if we are done */
 .if \ic != 0
 	isb
 .endif
-	dsb	ish
 	ret
 .endm