Date: Thu, 15 Jun 2023 15:13:28 GMT From: Warner Losh <imp@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 2d1d418e1e7b - main - mpi3mr: 3rd Generation Tri-Mode NVMe/SAS/SATA MegaRaid / eHBA Message-ID: <202306151513.35FFDSes053614@gitrepo.freebsd.org>
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The branch main has been updated by imp: URL: https://cgit.FreeBSD.org/src/commit/?id=2d1d418e1e7bc8325bb052185c17c81a674d0c4e commit 2d1d418e1e7bc8325bb052185c17c81a674d0c4e Author: Sumit Saxena <sumit.saxena@broadcom.com> AuthorDate: 2023-06-14 22:22:30 +0000 Commit: Warner Losh <imp@FreeBSD.org> CommitDate: 2023-06-15 14:52:40 +0000 mpi3mr: 3rd Generation Tri-Mode NVMe/SAS/SATA MegaRaid / eHBA This is Broadcom's mpi3mr driver for FreeBSD version 8.6.0.2.0. The mpi3mr driver supports Broadcom SAS4116-based cards in the 9600 series: 9670W-16i, 9670-24i, 9660-16i, 9620-16i, 9600-24i, 9600-16i, 9600W-16e, 9600-16e, 9600-8i8e. Initially only available as a module and on amd64/arm64, since that's how it has been tested to date. Future commits will add it to the kernel build and may expand the architectures it is supported on. Co-authored-by: Chandrakanth Patil <chandrakanth.patil@broadcom.com> Feedback-by: ken (prior versions) Reviewed-by: imp RelNotes: yes Differential-Revision: https://reviews.freebsd.org/D36771 Differential-Revision: https://reviews.freebsd.org/D36772 --- sys/dev/mpi3mr/mpi/mpi30_api.h | 57 + sys/dev/mpi3mr/mpi/mpi30_cnfg.h | 3839 +++++++++++++++++++++ sys/dev/mpi3mr/mpi/mpi30_image.h | 426 +++ sys/dev/mpi3mr/mpi/mpi30_init.h | 265 ++ sys/dev/mpi3mr/mpi/mpi30_ioc.h | 1615 +++++++++ sys/dev/mpi3mr/mpi/mpi30_pci.h | 97 + sys/dev/mpi3mr/mpi/mpi30_raid.h | 46 + sys/dev/mpi3mr/mpi/mpi30_sas.h | 99 + sys/dev/mpi3mr/mpi/mpi30_targ.h | 316 ++ sys/dev/mpi3mr/mpi/mpi30_tool.h | 476 +++ sys/dev/mpi3mr/mpi/mpi30_transport.h | 748 +++++ sys/dev/mpi3mr/mpi/mpi30_type.h | 99 + sys/dev/mpi3mr/mpi3mr.c | 6101 ++++++++++++++++++++++++++++++++++ sys/dev/mpi3mr/mpi3mr.h | 997 ++++++ sys/dev/mpi3mr/mpi3mr_app.c | 2206 ++++++++++++ sys/dev/mpi3mr/mpi3mr_app.h | 292 ++ sys/dev/mpi3mr/mpi3mr_cam.c | 2222 +++++++++++++ sys/dev/mpi3mr/mpi3mr_cam.h | 199 ++ sys/dev/mpi3mr/mpi3mr_pci.c | 698 ++++ sys/modules/Makefile | 6 + sys/modules/mpi3mr/Makefile | 13 + 21 files changed, 20817 insertions(+) diff --git a/sys/dev/mpi3mr/mpi/mpi30_api.h b/sys/dev/mpi3mr/mpi/mpi30_api.h new file mode 100644 index 000000000000..aa7b54ec470e --- /dev/null +++ b/sys/dev/mpi3mr/mpi/mpi30_api.h @@ -0,0 +1,57 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Support: <fbsd-storage-driver.pdl@broadcom.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * 3. Neither the name of the Broadcom Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing + * official policies,either expressed or implied, of the FreeBSD Project. + * + * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 + * + * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD + * + */ + +#ifndef MPI30_API_H +#define MPI30_API_H 1 + +#include "mpi30_type.h" +#include "mpi30_transport.h" +#include "mpi30_cnfg.h" +#include "mpi30_image.h" +#include "mpi30_init.h" +#include "mpi30_ioc.h" +#include "mpi30_pci.h" +#include "mpi30_raid.h" +#include "mpi30_sas.h" +#include "mpi30_targ.h" +#include "mpi30_tool.h" + +#endif /* MPI30_API_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_cnfg.h b/sys/dev/mpi3mr/mpi/mpi30_cnfg.h new file mode 100644 index 000000000000..d1ae2ebfa372 --- /dev/null +++ b/sys/dev/mpi3mr/mpi/mpi30_cnfg.h @@ -0,0 +1,3839 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Support: <fbsd-storage-driver.pdl@broadcom.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * 3. Neither the name of the Broadcom Inc. nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing + * official policies,either expressed or implied, of the FreeBSD Project. + * + * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 + * + * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD + * + */ + +#ifndef MPI30_CNFG_H +#define MPI30_CNFG_H 1 + +/***************************************************************************** + * Configuration Page Types * + ****************************************************************************/ +#define MPI3_CONFIG_PAGETYPE_IO_UNIT (0x00) +#define MPI3_CONFIG_PAGETYPE_MANUFACTURING (0x01) +#define MPI3_CONFIG_PAGETYPE_IOC (0x02) +#define MPI3_CONFIG_PAGETYPE_DRIVER (0x03) +#define MPI3_CONFIG_PAGETYPE_SECURITY (0x04) +#define MPI3_CONFIG_PAGETYPE_ENCLOSURE (0x11) +#define MPI3_CONFIG_PAGETYPE_DEVICE (0x12) +#define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT (0x20) +#define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER (0x21) +#define MPI3_CONFIG_PAGETYPE_SAS_PHY (0x23) +#define MPI3_CONFIG_PAGETYPE_SAS_PORT (0x24) +#define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT (0x30) +#define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31) +#define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33) + +/***************************************************************************** + * Configuration Page Attributes * + ****************************************************************************/ +#define MPI3_CONFIG_PAGEATTR_MASK (0xF0) +#define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00) +#define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10) +#define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20) + +/***************************************************************************** + * Configuration Page Actions * + ****************************************************************************/ +#define MPI3_CONFIG_ACTION_PAGE_HEADER (0x00) +#define MPI3_CONFIG_ACTION_READ_DEFAULT (0x01) +#define MPI3_CONFIG_ACTION_READ_CURRENT (0x02) +#define MPI3_CONFIG_ACTION_WRITE_CURRENT (0x03) +#define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04) +#define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05) + +/***************************************************************************** + * Configuration Page Addressing * + ****************************************************************************/ + +/**** Device PageAddress Format ****/ +#define MPI3_DEVICE_PGAD_FORM_MASK (0xF0000000) +#define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) +#define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000) +#define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) + +/**** SAS Expander PageAddress Format ****/ +#define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) +#define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) +#define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000) +#define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000) +#define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) +#define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) +#define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) + +/**** SAS Phy PageAddress Format ****/ +#define MPI3_SAS_PHY_PGAD_FORM_MASK (0xF0000000) +#define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) +#define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) + +/**** SAS Port PageAddress Format ****/ +#define MPI3_SASPORT_PGAD_FORM_MASK (0xF0000000) +#define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) +#define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) +#define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000FF) + +/**** Enclosure PageAddress Format ****/ +#define MPI3_ENCLOS_PGAD_FORM_MASK (0xF0000000) +#define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) +#define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000) +#define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) + +/**** PCIe Switch PageAddress Format ****/ +#define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) +#define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) +#define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000) +#define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000) +#define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) +#define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) +#define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) + +/**** PCIe Link PageAddress Format ****/ +#define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) +#define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) +#define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) +#define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000FF) + +/**** Security PageAddress Format ****/ +#define MPI3_SECURITY_PGAD_FORM_MASK (0xF0000000) +#define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000) +#define MPI3_SECURITY_PGAD_FORM_SLOT_NUM (0x10000000) +#define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000FF00) +#define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT (8) +#define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000FF) + +/***************************************************************************** + * Configuration Request Message * + ****************************************************************************/ +typedef struct _MPI3_CONFIG_REQUEST +{ + U16 HostTag; /* 0x00 */ + U8 IOCUseOnly02; /* 0x02 */ + U8 Function; /* 0x03 */ + U16 IOCUseOnly04; /* 0x04 */ + U8 IOCUseOnly06; /* 0x06 */ + U8 MsgFlags; /* 0x07 */ + U16 ChangeCount; /* 0x08 */ + U16 Reserved0A; /* 0x0A */ + U8 PageVersion; /* 0x0C */ + U8 PageNumber; /* 0x0D */ + U8 PageType; /* 0x0E */ + U8 Action; /* 0x0F */ + U32 PageAddress; /* 0x10 */ + U16 PageLength; /* 0x14 */ + U16 Reserved16; /* 0x16 */ + U32 Reserved18[2]; /* 0x18 */ + MPI3_SGE_UNION SGL; /* 0x20 */ +} MPI3_CONFIG_REQUEST, MPI3_POINTER PTR_MPI3_CONFIG_REQUEST, + Mpi3ConfigRequest_t, MPI3_POINTER pMpi3ConfigRequest_t; + +/***************************************************************************** + * Configuration Pages * + ****************************************************************************/ + +/***************************************************************************** + * Configuration Page Header * + ****************************************************************************/ +typedef struct _MPI3_CONFIG_PAGE_HEADER +{ + U8 PageVersion; /* 0x00 */ + U8 Reserved01; /* 0x01 */ + U8 PageNumber; /* 0x02 */ + U8 PageAttribute; /* 0x03 */ + U16 PageLength; /* 0x04 */ + U8 PageType; /* 0x06 */ + U8 Reserved07; /* 0x07 */ +} MPI3_CONFIG_PAGE_HEADER, MPI3_POINTER PTR_MPI3_CONFIG_PAGE_HEADER, + Mpi3ConfigPageHeader_t, MPI3_POINTER pMpi3ConfigPageHeader_t; + +/***************************************************************************** + * Common definitions used by Configuration Pages * + ****************************************************************************/ + +/**** Defines for Negotiated Link Rates ****/ +#define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xF0) +#define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4) +#define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0F) +#define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT (0) +/*** Below defines are used in both the PhysicalLinkRate and ***/ +/*** LogicalLinkRate fields above. ***/ +/*** (by applying the proper _SHIFT value) ***/ +#define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) +#define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) +#define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) +#define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) +#define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) +#define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) +#define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) +#define MPI3_SAS_NEG_LINK_RATE_1_5 (0x08) +#define MPI3_SAS_NEG_LINK_RATE_3_0 (0x09) +#define MPI3_SAS_NEG_LINK_RATE_6_0 (0x0A) +#define MPI3_SAS_NEG_LINK_RATE_12_0 (0x0B) +#define MPI3_SAS_NEG_LINK_RATE_22_5 (0x0C) + +/**** Defines for the AttachedPhyInfo field ****/ +#define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) +#define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) +#define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) + +#define MPI3_SAS_APHYINFO_REASON_MASK (0x0000000F) +#define MPI3_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) +#define MPI3_SAS_APHYINFO_REASON_POWER_ON (0x00000001) +#define MPI3_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) +#define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) +#define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) +#define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) +#define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) +#define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) +#define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) +#define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC (0x00000009) + +/**** Defines for the PhyInfo field ****/ +#define MPI3_SAS_PHYINFO_STATUS_MASK (0xC0000000) +#define MPI3_SAS_PHYINFO_STATUS_SHIFT (30) +#define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE (0x00000000) +#define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST (0x40000000) +#define MPI3_SAS_PHYINFO_STATUS_VACANT (0x80000000) + +#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) +#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000) +#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000) +#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000) + +#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK (0x04000000) +#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26) +#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK (0x02000000) +#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT (25) +#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK (0x01000000) +#define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT (24) + +#define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) +#define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN (0x00200000) +#define MPI3_SAS_PHYINFO_ZONING_ENABLED (0x00100000) + +#define MPI3_SAS_PHYINFO_REASON_MASK (0x000F0000) +#define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) +#define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000) +#define MPI3_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) +#define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) +#define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) +#define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) +#define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) +#define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) +#define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) +#define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC (0x00090000) + +#define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) +#define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) +#define MPI3_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) + +#define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK (0x00000F00) +#define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT (8) + +#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK (0x000000F0) +#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT (0x00000000) +#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE (0x00000010) +#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE (0x00000020) + +/**** Defines for the ProgrammedLinkRate field ****/ +#define MPI3_SAS_PRATE_MAX_RATE_MASK (0xF0) +#define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) +#define MPI3_SAS_PRATE_MAX_RATE_1_5 (0x80) +#define MPI3_SAS_PRATE_MAX_RATE_3_0 (0x90) +#define MPI3_SAS_PRATE_MAX_RATE_6_0 (0xA0) +#define MPI3_SAS_PRATE_MAX_RATE_12_0 (0xB0) +#define MPI3_SAS_PRATE_MAX_RATE_22_5 (0xC0) +#define MPI3_SAS_PRATE_MIN_RATE_MASK (0x0F) +#define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) +#define MPI3_SAS_PRATE_MIN_RATE_1_5 (0x08) +#define MPI3_SAS_PRATE_MIN_RATE_3_0 (0x09) +#define MPI3_SAS_PRATE_MIN_RATE_6_0 (0x0A) +#define MPI3_SAS_PRATE_MIN_RATE_12_0 (0x0B) +#define MPI3_SAS_PRATE_MIN_RATE_22_5 (0x0C) + +/**** Defines for the HwLinkRate field ****/ +#define MPI3_SAS_HWRATE_MAX_RATE_MASK (0xF0) +#define MPI3_SAS_HWRATE_MAX_RATE_1_5 (0x80) +#define MPI3_SAS_HWRATE_MAX_RATE_3_0 (0x90) +#define MPI3_SAS_HWRATE_MAX_RATE_6_0 (0xA0) +#define MPI3_SAS_HWRATE_MAX_RATE_12_0 (0xB0) +#define MPI3_SAS_HWRATE_MAX_RATE_22_5 (0xC0) +#define MPI3_SAS_HWRATE_MIN_RATE_MASK (0x0F) +#define MPI3_SAS_HWRATE_MIN_RATE_1_5 (0x08) +#define MPI3_SAS_HWRATE_MIN_RATE_3_0 (0x09) +#define MPI3_SAS_HWRATE_MIN_RATE_6_0 (0x0A) +#define MPI3_SAS_HWRATE_MIN_RATE_12_0 (0x0B) +#define MPI3_SAS_HWRATE_MIN_RATE_22_5 (0x0C) + +/**** Defines for the Slot field ****/ +#define MPI3_SLOT_INVALID (0xFFFF) + +/**** Defines for the SlotIndex field ****/ +#define MPI3_SLOT_INDEX_INVALID (0xFFFF) + +/**** Defines for the LinkChangeCount fields ****/ +#define MPI3_LINK_CHANGE_COUNT_INVALID (0xFFFF) + +/**** Defines for the RateChangeCount fields ****/ +#define MPI3_RATE_CHANGE_COUNT_INVALID (0xFFFF) + +/**** Defines for the Temp Sensor Location field ****/ +#define MPI3_TEMP_SENSOR_LOCATION_INTERNAL (0x0) +#define MPI3_TEMP_SENSOR_LOCATION_INLET (0x1) +#define MPI3_TEMP_SENSOR_LOCATION_OUTLET (0x2) +#define MPI3_TEMP_SENSOR_LOCATION_DRAM (0x3) + +/***************************************************************************** + * Manufacturing Configuration Pages * + ****************************************************************************/ + +#define MPI3_MFGPAGE_VENDORID_BROADCOM (0x1000) + +/* MPI v3.0 SAS Products */ +#define MPI3_MFGPAGE_DEVID_SAS4116 (0x00A5) +#define MPI3_MFGPAGE_DEVID_SAS5116_MPI (0x00B3) +#define MPI3_MFGPAGE_DEVID_SAS5116_NVME (0x00B4) +#define MPI3_MFGPAGE_DEVID_SAS5116_MPI_NS (0x00B5) +#define MPI3_MFGPAGE_DEVID_SAS5116_NVME_NS (0x00B6) +#define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH (0x00B8) + +/***************************************************************************** + * Manufacturing Page 0 * + ****************************************************************************/ +typedef struct _MPI3_MAN_PAGE0 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U8 ChipRevision[8]; /* 0x08 */ + U8 ChipName[32]; /* 0x10 */ + U8 BoardName[32]; /* 0x30 */ + U8 BoardAssembly[32]; /* 0x50 */ + U8 BoardTracerNumber[32]; /* 0x70 */ + U32 BoardPower; /* 0x90 */ + U32 Reserved94; /* 0x94 */ + U32 Reserved98; /* 0x98 */ + U8 OEM; /* 0x9C */ + U8 ProfileIdentifier; /* 0x9D */ + U16 Flags; /* 0x9E */ + U8 BoardMfgDay; /* 0xA0 */ + U8 BoardMfgMonth; /* 0xA1 */ + U16 BoardMfgYear; /* 0xA2 */ + U8 BoardReworkDay; /* 0xA4 */ + U8 BoardReworkMonth; /* 0xA5 */ + U16 BoardReworkYear; /* 0xA6 */ + U8 BoardRevision[8]; /* 0xA8 */ + U8 EPackFRU[16]; /* 0xB0 */ + U8 ProductName[256]; /* 0xC0 */ +} MPI3_MAN_PAGE0, MPI3_POINTER PTR_MPI3_MAN_PAGE0, + Mpi3ManPage0_t, MPI3_POINTER pMpi3ManPage0_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_MAN0_PAGEVERSION (0x00) + +/**** Defines for the Flags field ****/ +#define MPI3_MAN0_FLAGS_SWITCH_PRESENT (0x0002) +#define MPI3_MAN0_FLAGS_EXPANDER_PRESENT (0x0001) + +/***************************************************************************** + * Manufacturing Page 1 * + ****************************************************************************/ + +#define MPI3_MAN1_VPD_SIZE (512) + +typedef struct _MPI3_MAN_PAGE1 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U32 Reserved08[2]; /* 0x08 */ + U8 VPD[MPI3_MAN1_VPD_SIZE]; /* 0x10 */ +} MPI3_MAN_PAGE1, MPI3_POINTER PTR_MPI3_MAN_PAGE1, + Mpi3ManPage1_t, MPI3_POINTER pMpi3ManPage1_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_MAN1_PAGEVERSION (0x00) + + +/***************************************************************************** + * Manufacturing Page 2 * + ****************************************************************************/ + +typedef struct _MPI3_MAN_PAGE2 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U8 Flags; /* 0x08 */ + U8 Reserved09[3]; /* 0x09 */ + U32 Reserved0C[3]; /* 0x0C */ + U8 OEMBoardTracerNumber[32]; /* 0x18 */ +} MPI3_MAN_PAGE2, MPI3_POINTER PTR_MPI3_MAN_PAGE2, + Mpi3ManPage2_t, MPI3_POINTER pMpi3ManPage2_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_MAN2_PAGEVERSION (0x00) + +/**** Defines for the Flags field ****/ +#define MPI3_MAN2_FLAGS_TRACER_PRESENT (0x01) + +/***************************************************************************** + * Manufacturing Page 5 * + ****************************************************************************/ +typedef struct _MPI3_MAN5_PHY_ENTRY +{ + U64 IOC_WWID; /* 0x00 */ + U64 DeviceName; /* 0x08 */ + U64 SATA_WWID; /* 0x10 */ +} MPI3_MAN5_PHY_ENTRY, MPI3_POINTER PTR_MPI3_MAN5_PHY_ENTRY, + Mpi3Man5PhyEntry_t, MPI3_POINTER pMpi3Man5PhyEntry_t; + +#ifndef MPI3_MAN5_PHY_MAX +#define MPI3_MAN5_PHY_MAX (1) +#endif /* MPI3_MAN5_PHY_MAX */ + +typedef struct _MPI3_MAN_PAGE5 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U8 NumPhys; /* 0x08 */ + U8 Reserved09[3]; /* 0x09 */ + U32 Reserved0C; /* 0x0C */ + MPI3_MAN5_PHY_ENTRY Phy[MPI3_MAN5_PHY_MAX]; /* 0x10 */ +} MPI3_MAN_PAGE5, MPI3_POINTER PTR_MPI3_MAN_PAGE5, + Mpi3ManPage5_t, MPI3_POINTER pMpi3ManPage5_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_MAN5_PAGEVERSION (0x00) + +/***************************************************************************** + * Manufacturing Page 6 * + ****************************************************************************/ +typedef struct _MPI3_MAN6_GPIO_ENTRY +{ + U8 FunctionCode; /* 0x00 */ + U8 FunctionFlags; /* 0x01 */ + U16 Flags; /* 0x02 */ + U8 Param1; /* 0x04 */ + U8 Param2; /* 0x05 */ + U16 Reserved06; /* 0x06 */ + U32 Param3; /* 0x08 */ +} MPI3_MAN6_GPIO_ENTRY, MPI3_POINTER PTR_MPI3_MAN6_GPIO_ENTRY, + Mpi3Man6GpioEntry_t, MPI3_POINTER pMpi3Man6GpioEntry_t; + +/**** Defines for the FunctionCode field ****/ +#define MPI3_MAN6_GPIO_FUNCTION_GENERIC (0x00) +#define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE (0x01) +#define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT (0x02) +#define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY (0x03) +#define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE (0x04) +#define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN (0x05) +#define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW (0x06) +#define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT (0x07) +#define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE (0x08) +#define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET (0x0A) +#define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET (0x0B) +#define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT (0x0C) +#define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE (0x0D) +#define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE (0x0E) +#define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT (0x0F) +#define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE (0x10) +#define MPI3_MAN6_GPIO_FUNCTION_LICENSE (0x11) +#define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL (0x12) +#define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP (0x13) +#define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER (0x14) +#define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY (0x15) +#define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL (0x16) +#define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT (0x17) +#define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE (0x18) +#define MPI3_MAN6_GPIO_FUNCTION_MGMT_CONTROLLER_RESET (0x19) + +/**** Defines for FunctionFlags when FunctionCode is ISTWI_RESET ****/ +#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK (0x01) +#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI (0x00) +#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID (0x01) + +/**** Defines for Param1 (Flags) when FunctionCode is EXT_INTERRUPT ****/ +#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK (0xF0) +#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00) +#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10) +#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20) + +#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01) +#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00) +#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01) + +/**** Defines for Param1 (PHY STATE) when FunctionCode is PORT_STATUS_GREEN ****/ +#define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00) +#define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01) + +/**** Defines for Param1 (INTERFACE_SIGNAL) when FunctionCode is CABLE_MANAGEMENT ****/ +#define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00) +#define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE (0x01) +#define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE (0x02) + +/**** Defines for Param1 (LICENSE_TYPE) when FunctionCode is LICENSE ****/ +#define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON (0x00) + + +/**** Defines for the Flags field ****/ +#define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK (0x0100) +#define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE (0x0100) +#define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE (0x0000) +#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK (0x00C0) +#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM (0x0000) +#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM (0x0040) +#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM (0x0080) +#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM (0x00C0) +#define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK (0x0030) +#define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT (4) +#define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH (0x0008) +#define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED (0x0004) +#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK (0x0003) +#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT (0x0000) +#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT (0x0001) +#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT (0x0002) +#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT (0x0003) + +#ifndef MPI3_MAN6_GPIO_MAX +#define MPI3_MAN6_GPIO_MAX (1) +#endif /* MPI3_MAN6_GPIO_MAX */ + +typedef struct _MPI3_MAN_PAGE6 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U16 Flags; /* 0x08 */ + U16 Reserved0A; /* 0x0A */ + U8 NumGPIO; /* 0x0C */ + U8 Reserved0D[3]; /* 0x0D */ + MPI3_MAN6_GPIO_ENTRY GPIO[MPI3_MAN6_GPIO_MAX]; /* 0x10 */ +} MPI3_MAN_PAGE6, MPI3_POINTER PTR_MPI3_MAN_PAGE6, + Mpi3ManPage6_t, MPI3_POINTER pMpi3ManPage6_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_MAN6_PAGEVERSION (0x00) + +/**** Defines for the Flags field ****/ +#define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED (0x0001) + +/***************************************************************************** + * Manufacturing Page 7 * + ****************************************************************************/ +typedef struct _MPI3_MAN7_RECEPTACLE_INFO +{ + U32 Name[4]; /* 0x00 */ + U8 Location; /* 0x10 */ + U8 ConnectorType; /* 0x11 */ + U8 PEDClk; /* 0x12 */ + U8 ConnectorID; /* 0x13 */ + U32 Reserved14; /* 0x14 */ +} MPI3_MAN7_RECEPTACLE_INFO, MPI3_POINTER PTR_MPI3_MAN7_RECEPTACLE_INFO, + Mpi3Man7ReceptacleInfo_t, MPI3_POINTER pMpi3Man7ReceptacleInfo_t; + +/**** Defines for Location field ****/ +#define MPI3_MAN7_LOCATION_UNKNOWN (0x00) +#define MPI3_MAN7_LOCATION_INTERNAL (0x01) +#define MPI3_MAN7_LOCATION_EXTERNAL (0x02) +#define MPI3_MAN7_LOCATION_VIRTUAL (0x03) +#define MPI3_MAN7_LOCATION_HOST (0x04) + +/**** Defines for ConnectorType - Use definitions from SES-4 ****/ +#define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO (0x00) + +/**** Defines for PEDClk field ****/ +#define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10) +#define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00) +#define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10) +#define MPI3_MAN7_PEDCLK_ID_MASK (0x0F) + +#ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX +#define MPI3_MAN7_RECEPTACLE_INFO_MAX (1) +#endif /* MPI3_MAN7_RECEPTACLE_INFO_MAX */ + +typedef struct _MPI3_MAN_PAGE7 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U32 Flags; /* 0x08 */ + U8 NumReceptacles; /* 0x0C */ + U8 Reserved0D[3]; /* 0x0D */ + U32 EnclosureName[4]; /* 0x10 */ + MPI3_MAN7_RECEPTACLE_INFO ReceptacleInfo[MPI3_MAN7_RECEPTACLE_INFO_MAX]; /* 0x20 */ /* variable length array */ +} MPI3_MAN_PAGE7, MPI3_POINTER PTR_MPI3_MAN_PAGE7, + Mpi3ManPage7_t, MPI3_POINTER pMpi3ManPage7_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_MAN7_PAGEVERSION (0x00) + +/**** Defines for Flags field ****/ +#define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK (0x01) +#define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 (0x00) +#define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 (0x01) + + +/***************************************************************************** + * Manufacturing Page 8 * + ****************************************************************************/ + +typedef struct _MPI3_MAN8_PHY_INFO +{ + U8 ReceptacleID; /* 0x00 */ + U8 ConnectorLane; /* 0x01 */ + U16 Reserved02; /* 0x02 */ + U16 Slotx1; /* 0x04 */ + U16 Slotx2; /* 0x06 */ + U16 Slotx4; /* 0x08 */ + U16 Reserved0A; /* 0x0A */ + U32 Reserved0C; /* 0x0C */ +} MPI3_MAN8_PHY_INFO, MPI3_POINTER PTR_MPI3_MAN8_PHY_INFO, + Mpi3Man8PhyInfo_t, MPI3_POINTER pMpi3Man8PhyInfo_t; + +/**** Defines for ReceptacleID field ****/ +#define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED (0xFF) + +/**** Defines for ConnectorLane field ****/ +#define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED (0xFF) + +#ifndef MPI3_MAN8_PHY_INFO_MAX +#define MPI3_MAN8_PHY_INFO_MAX (1) +#endif /* MPI3_MAN8_PHY_INFO_MAX */ + +typedef struct _MPI3_MAN_PAGE8 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U32 Reserved08; /* 0x08 */ + U8 NumPhys; /* 0x0C */ + U8 Reserved0D[3]; /* 0x0D */ + MPI3_MAN8_PHY_INFO PhyInfo[MPI3_MAN8_PHY_INFO_MAX]; /* 0x10 */ /* variable length array */ +} MPI3_MAN_PAGE8, MPI3_POINTER PTR_MPI3_MAN_PAGE8, + Mpi3ManPage8_t, MPI3_POINTER pMpi3ManPage8_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_MAN8_PAGEVERSION (0x00) + +/***************************************************************************** + * Manufacturing Page 9 * + ****************************************************************************/ +typedef struct _MPI3_MAN9_RSRC_ENTRY +{ + U32 Maximum; /* 0x00 */ + U32 Decrement; /* 0x04 */ + U32 Minimum; /* 0x08 */ + U32 Actual; /* 0x0C */ +} MPI3_MAN9_RSRC_ENTRY, MPI3_POINTER PTR_MPI3_MAN9_RSRC_ENTRY, + Mpi3Man9RsrcEntry_t, MPI3_POINTER pMpi3Man9RsrcEntry_t; + +typedef enum _MPI3_MAN9_RESOURCES +{ + MPI3_MAN9_RSRC_OUTSTANDING_REQS = 0, + MPI3_MAN9_RSRC_TARGET_CMDS = 1, + MPI3_MAN9_RSRC_RESERVED02 = 2, + MPI3_MAN9_RSRC_NVME = 3, + MPI3_MAN9_RSRC_INITIATORS = 4, + MPI3_MAN9_RSRC_VDS = 5, + MPI3_MAN9_RSRC_ENCLOSURES = 6, + MPI3_MAN9_RSRC_ENCLOSURE_PHYS = 7, + MPI3_MAN9_RSRC_EXPANDERS = 8, + MPI3_MAN9_RSRC_PCIE_SWITCHES = 9, + MPI3_MAN9_RSRC_RESERVED10 = 10, + MPI3_MAN9_RSRC_HOST_PD_DRIVES = 11, + MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES = 12, + MPI3_MAN9_RSRC_RAID_PD_DRIVES = 13, + MPI3_MAN9_RSRC_DRV_DIAG_BUF = 14, + MPI3_MAN9_RSRC_NAMESPACE_COUNT = 15, + MPI3_MAN9_RSRC_NUM_RESOURCES +} MPI3_MAN9_RESOURCES; + +#define MPI3_MAN9_MIN_OUTSTANDING_REQS (1) +#define MPI3_MAN9_MAX_OUTSTANDING_REQS (65000) + +#define MPI3_MAN9_MIN_TARGET_CMDS (0) +#define MPI3_MAN9_MAX_TARGET_CMDS (65535) + +#define MPI3_MAN9_MIN_NVME_TARGETS (0) +/* Max NVMe Targets is product specific */ + +#define MPI3_MAN9_MIN_INITIATORS (0) +/* Max Initiators is product specific */ + +#define MPI3_MAN9_MIN_VDS (0) +/* Max VDs is product specific */ + +#define MPI3_MAN9_MIN_ENCLOSURES (1) +#define MPI3_MAN9_MAX_ENCLOSURES (65535) + +#define MPI3_MAN9_MIN_ENCLOSURE_PHYS (0) +/* Max Enclosure Phys is product specific */ + +#define MPI3_MAN9_MIN_EXPANDERS (0) +#define MPI3_MAN9_MAX_EXPANDERS (65535) + +#define MPI3_MAN9_MIN_PCIE_SWITCHES (0) +/* Max PCIe Switches is product specific */ + +#define MPI3_MAN9_MIN_HOST_PD_DRIVES (0) +/* Max Host PD Drives is product specific */ + +#define MPI3_MAN9_ADV_HOST_PD_DRIVES (0) +/* Max Advanced Host PD Drives is product specific */ + +#define MPI3_MAN9_RAID_PD_DRIVES (0) +/* Max RAID PD Drives is product specific */ + +#define MPI3_MAN9_DRIVER_DIAG_BUFFER (0) +/* Max Driver Diag Buffer is product specific */ + +#define MPI3_MAN9_MIN_NAMESPACE_COUNT (1) + +#define MPI3_MAN9_MIN_EXPANDERS (0) +#define MPI3_MAN9_MAX_EXPANDERS (65535) + + +typedef struct _MPI3_MAN_PAGE9 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U8 NumResources; /* 0x08 */ + U8 Reserved09; /* 0x09 */ + U16 Reserved0A; /* 0x0A */ + U32 Reserved0C; /* 0x0C */ + U32 Reserved10; /* 0x10 */ + U32 Reserved14; /* 0x14 */ + U32 Reserved18; /* 0x18 */ + U32 Reserved1C; /* 0x1C */ + MPI3_MAN9_RSRC_ENTRY Resource[MPI3_MAN9_RSRC_NUM_RESOURCES]; /* 0x20 */ +} MPI3_MAN_PAGE9, MPI3_POINTER PTR_MPI3_MAN_PAGE9, + Mpi3ManPage9_t, MPI3_POINTER pMpi3ManPage9_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_MAN9_PAGEVERSION (0x00) + +/***************************************************************************** + * Manufacturing Page 10 * + ****************************************************************************/ +typedef struct _MPI3_MAN10_ISTWI_CTRLR_ENTRY +{ + U16 TargetAddress; /* 0x00 */ + U16 Flags; /* 0x02 */ + U8 SCLLowOverride; /* 0x04 */ + U8 SCLHighOverride; /* 0x05 */ + U16 Reserved06; /* 0x06 */ +} MPI3_MAN10_ISTWI_CTRLR_ENTRY, MPI3_POINTER PTR_MPI3_MAN10_ISTWI_CTRLR_ENTRY, + Mpi3Man10IstwiCtrlrEntry_t, MPI3_POINTER pMpi3Man10IstwiCtrlrEntry_t; + +/**** Defines for the Flags field ****/ + +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_MASK (0xC000) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_SHIFT (14) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_50_NS (0x0000) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_10_NS (0x4000) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_5_NS (0x8000) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_0_NS (0xC000) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_MASK (0x3000) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_SHIFT (12) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_I2C (0x0000) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_I3C (0x1000) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_AUTO (0x2000) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_MASK (0x0E00) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_SHIFT (9) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_12_5_MHZ (0x0000) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_8_MHZ (0x0200) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_6_MHZ (0x0400) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_4_MHZ (0x0600) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_2_MHZ (0x0800) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000C) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_SHIFT (0) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100_KHZ (0x0000) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400_KHZ (0x0004) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED (0x0002) +#define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED (0x0001) + +#ifndef MPI3_MAN10_ISTWI_CTRLR_MAX +#define MPI3_MAN10_ISTWI_CTRLR_MAX (1) +#endif /* MPI3_MAN10_ISTWI_CTRLR_MAX */ + +typedef struct _MPI3_MAN_PAGE10 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U32 Reserved08; /* 0x08 */ + U8 NumISTWICtrl; /* 0x0C */ + U8 Reserved0D[3]; /* 0x0D */ + MPI3_MAN10_ISTWI_CTRLR_ENTRY ISTWIController[MPI3_MAN10_ISTWI_CTRLR_MAX]; /* 0x10 */ +} MPI3_MAN_PAGE10, MPI3_POINTER PTR_MPI3_MAN_PAGE10, + Mpi3ManPage10_t, MPI3_POINTER pMpi3ManPage10_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_MAN10_PAGEVERSION (0x00) + +/***************************************************************************** + * Manufacturing Page 11 * + ****************************************************************************/ +typedef struct _MPI3_MAN11_MUX_DEVICE_FORMAT +{ + U8 MaxChannel; /* 0x00 */ + U8 Reserved01[3]; /* 0x01 */ + U32 Reserved04; /* 0x04 */ +} MPI3_MAN11_MUX_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_MUX_DEVICE_FORMAT, + Mpi3Man11MuxDeviceFormat_t, MPI3_POINTER pMpi3Man11MuxDeviceFormat_t; + +typedef struct _MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT +{ + U8 Type; /* 0x00 */ + U8 Reserved01[3]; /* 0x01 */ + U8 TempChannel[4]; /* 0x04 */ +} MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT, + Mpi3Man11TempSensorDeviceFormat_t, MPI3_POINTER pMpi3Man11TempSensorDeviceFormat_t; + +/**** Defines for the Type field ****/ +#define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654 (0x00) +#define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442 (0x01) +#define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476 (0x02) +#define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B (0x03) + +/**** Define for the TempChannel field ****/ +#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK (0xE0) +#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT (5) +/**** for the Location field values - use MPI3_TEMP_SENSOR_LOCATION_ defines ****/ +#define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED (0x01) + + +typedef struct _MPI3_MAN11_SEEPROM_DEVICE_FORMAT +{ + U8 Size; /* 0x00 */ + U8 PageWriteSize; /* 0x01 */ + U16 Reserved02; /* 0x02 */ + U32 Reserved04; /* 0x04 */ +} MPI3_MAN11_SEEPROM_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_SEEPROM_DEVICE_FORMAT, + Mpi3Man11SeepromDeviceFormat_t, MPI3_POINTER pMpi3Man11SeepromDeviceFormat_t; + +/**** Defines for the Size field ****/ +#define MPI3_MAN11_SEEPROM_SIZE_1KBITS (0x01) +#define MPI3_MAN11_SEEPROM_SIZE_2KBITS (0x02) +#define MPI3_MAN11_SEEPROM_SIZE_4KBITS (0x03) +#define MPI3_MAN11_SEEPROM_SIZE_8KBITS (0x04) +#define MPI3_MAN11_SEEPROM_SIZE_16KBITS (0x05) +#define MPI3_MAN11_SEEPROM_SIZE_32KBITS (0x06) +#define MPI3_MAN11_SEEPROM_SIZE_64KBITS (0x07) +#define MPI3_MAN11_SEEPROM_SIZE_128KBITS (0x08) + +typedef struct _MPI3_MAN11_DDR_SPD_DEVICE_FORMAT +{ + U8 Channel; /* 0x00 */ + U8 Reserved01[3]; /* 0x01 */ + U32 Reserved04; /* 0x04 */ +} MPI3_MAN11_DDR_SPD_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_DDR_SPD_DEVICE_FORMAT, + Mpi3Man11DdrSpdDeviceFormat_t, MPI3_POINTER pMpi3Man11DdrSpdDeviceFormat_t; + +typedef struct _MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT +{ + U8 Type; /* 0x00 */ + U8 ReceptacleID; /* 0x01 */ + U16 Reserved02; /* 0x02 */ + U32 Reserved04; /* 0x04 */ +} MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT, + Mpi3Man11CableMgmtDeviceFormat_t, MPI3_POINTER pMpi3Man11CableMgmtDeviceFormat_t; + +/**** Defines for the Type field ****/ +#define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636 (0x00) + +typedef struct _MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT +{ + U16 Flags; /* 0x00 */ *** 20019 LINES SKIPPED ***
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