From owner-svn-src-all@freebsd.org Wed Sep 21 05:22:50 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id BA1B6BE35B5; Wed, 21 Sep 2016 05:22:50 +0000 (UTC) (envelope-from wma@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 72786DD6; Wed, 21 Sep 2016 05:22:50 +0000 (UTC) (envelope-from wma@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u8L5Mnod082999; Wed, 21 Sep 2016 05:22:49 GMT (envelope-from wma@FreeBSD.org) Received: (from wma@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u8L5Mn31082998; Wed, 21 Sep 2016 05:22:49 GMT (envelope-from wma@FreeBSD.org) Message-Id: <201609210522.u8L5Mn31082998@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: wma set sender to wma@FreeBSD.org using -f From: Wojciech Macek Date: Wed, 21 Sep 2016 05:22:49 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r306069 - head/sys/arm64/arm64 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Sep 2016 05:22:50 -0000 Author: wma Date: Wed Sep 21 05:22:49 2016 New Revision: 306069 URL: https://svnweb.freebsd.org/changeset/base/306069 Log: Add support for SPI-mapped MSI interrupts in GICv3. PIC_SETUP_INTR implementation in GICv3 did not allow for setting up interrupts without included FDT description. GICv2m-like MSI interrupts, which map MSI messages to SPI interrupt lines, may not have a description in FDT. Add support for such interrupts by setting the trigger and polarity to the appropriate values for MSI (edge, high) and get the hardware IRQ number from the corresponding ISRC. Obtained from: Semihalf Submitted by: Michal Stanek Sponsored by: Annapurna Labs Reviewed by: wma Differential Revision: https://reviews.freebsd.org/D7662 Modified: head/sys/arm64/arm64/gic_v3.c Modified: head/sys/arm64/arm64/gic_v3.c ============================================================================== --- head/sys/arm64/arm64/gic_v3.c Wed Sep 21 05:15:50 2016 (r306068) +++ head/sys/arm64/arm64/gic_v3.c Wed Sep 21 05:22:49 2016 (r306069) @@ -503,12 +503,33 @@ gic_map_fdt(device_t dev, u_int ncells, #endif static int +gic_map_msi(device_t dev, struct intr_map_data_msi *msi_data, u_int *irqp, + enum intr_polarity *polp, enum intr_trigger *trigp) +{ + struct gic_v3_irqsrc *gi; + + /* SPI-mapped MSI */ + gi = (struct gic_v3_irqsrc *)msi_data->isrc; + if (gi == NULL) + return (ENXIO); + + *irqp = gi->gi_irq; + + /* MSI/MSI-X interrupts are always edge triggered with high polarity */ + *polp = INTR_POLARITY_HIGH; + *trigp = INTR_TRIGGER_EDGE; + + return (0); +} + +static int do_gic_v3_map_intr(device_t dev, struct intr_map_data *data, u_int *irqp, enum intr_polarity *polp, enum intr_trigger *trigp) { struct gic_v3_softc *sc; enum intr_polarity pol; enum intr_trigger trig; + struct intr_map_data_msi *dam; #ifdef FDT struct intr_map_data_fdt *daf; #endif @@ -525,6 +546,12 @@ do_gic_v3_map_intr(device_t dev, struct return (EINVAL); break; #endif + case INTR_MAP_DATA_MSI: + /* SPI-mapped MSI */ + dam = (struct intr_map_data_msi *)data; + if (gic_map_msi(dev, dam, &irq, &pol, &trig) != 0) + return (EINVAL); + break; default: return (EINVAL); }