From owner-svn-src-stable@freebsd.org Tue Oct 24 06:49:08 2017 Return-Path: Delivered-To: svn-src-stable@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 5E33AE42486; Tue, 24 Oct 2017 06:49:08 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 3A20972BF8; Tue, 24 Oct 2017 06:49:08 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v9O6n77R099329; Tue, 24 Oct 2017 06:49:07 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v9O6n72b099327; Tue, 24 Oct 2017 06:49:07 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201710240649.v9O6n72b099327@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Tue, 24 Oct 2017 06:49:07 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r324946 - stable/11/contrib/llvm/lib/Target/AArch64 X-SVN-Group: stable-11 X-SVN-Commit-Author: dim X-SVN-Commit-Paths: stable/11/contrib/llvm/lib/Target/AArch64 X-SVN-Commit-Revision: 324946 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Oct 2017 06:49:08 -0000 Author: dim Date: Tue Oct 24 06:49:06 2017 New Revision: 324946 URL: https://svnweb.freebsd.org/changeset/base/324946 Log: MFC r324826: Pull in r316035 from upstream llvm trunk (by Tim Northover): AArch64: account for possible frame index operand in compares. If the address of a local is used in a comparison, AArch64 can fold the address-calculation into the comparison via "adds". Unfortunately, a couple of places (both hit in this one test) are not ready to deal with that yet and just assume the first source operand is a register. This should fix an assertion failure while building the test suite of www/firefox for AArch64. PR: 223048 Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp stable/11/contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp Directory Properties: stable/11/ (props changed) Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp Tue Oct 24 05:41:48 2017 (r324945) +++ stable/11/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp Tue Oct 24 06:49:06 2017 (r324946) @@ -940,6 +940,12 @@ bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const { + // The first operand can be a frame index where we'd normally expect a + // register. + assert(MI.getNumOperands() >= 2 && "All AArch64 cmps should have 2 operands"); + if (!MI.getOperand(1).isReg()) + return false; + switch (MI.getOpcode()) { default: break; Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp ============================================================================== --- stable/11/contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp Tue Oct 24 05:41:48 2017 (r324945) +++ stable/11/contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp Tue Oct 24 06:49:06 2017 (r324946) @@ -167,6 +167,9 @@ AArch64RedundantCopyElimination::knownRegValInBlock( // CMP is an alias for SUBS with a dead destination register. case AArch64::SUBSWri: case AArch64::SUBSXri: { + // Sometimes the first operand is a FrameIndex. Bail if tht happens. + if (!PredI.getOperand(1).isReg()) + return None; MCPhysReg SrcReg = PredI.getOperand(1).getReg(); // Must not be a symbolic immediate.