From owner-cvs-src@FreeBSD.ORG Sat Jun 28 18:38:58 2003 Return-Path: Delivered-To: cvs-src@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 1EFB737B401; Sat, 28 Jun 2003 18:38:58 -0700 (PDT) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id C09204400D; Sat, 28 Jun 2003 18:38:57 -0700 (PDT) (envelope-from wpaul@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.12.6/8.12.6) with ESMTP id h5T1cv0U081190; Sat, 28 Jun 2003 18:38:57 -0700 (PDT) (envelope-from wpaul@repoman.freebsd.org) Received: (from wpaul@localhost) by repoman.freebsd.org (8.12.6/8.12.6/Submit) id h5T1cv1s081189; Sat, 28 Jun 2003 18:38:57 -0700 (PDT) Message-Id: <200306290138.h5T1cv1s081189@repoman.freebsd.org> From: Bill Paul Date: Sat, 28 Jun 2003 18:38:57 -0700 (PDT) To: src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org X-FreeBSD-CVS-Branch: HEAD Subject: cvs commit: src/sys/pci if_xl.c X-BeenThere: cvs-src@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Jun 2003 01:38:58 -0000 wpaul 2003/06/28 18:38:57 PDT FreeBSD src repository Modified files: sys/pci if_xl.c Log: Modify the xl_reset() routine slightly so that, if we're using memory mapped I/O mode, we pause for .1 seconds after issuing the reset command before trying to poll the 'command busy' bit in the status register. With my 3c575C cardbus NIC, my Sony Picturebook locks up when it tries to read the status register immediately after the reset. This appears to be a problem only with certain NICs on certain hardware, but the added delay should not hurt cards that already work. This bug seems to have been brought to light by the fact that the xl driver now defaults to memory mapped I/O mode instead of programmed I/O mode like it used to. With PIO mode, the delay isn't needed and everything works (which is why this NIC worked with 5.0-RELEASE but not 5.1). I suspect that what's happening is that when the chip is reset, it takes a little while for the memory-mapped decoding logic to recover. Trying to access the chip's registers during this period causes an error condition of some kind that wedges the system. Revision Changes Path 1.145 +10 -0 src/sys/pci/if_xl.c