From owner-svn-src-head@freebsd.org Fri May 4 19:28:06 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 306CBFB5DB9; Fri, 4 May 2018 19:28:06 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id D85647B454; Fri, 4 May 2018 19:28:05 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id B527D13240; Fri, 4 May 2018 19:28:05 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w44JS51i094032; Fri, 4 May 2018 19:28:05 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w44JS5vo094031; Fri, 4 May 2018 19:28:05 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201805041928.w44JS5vo094031@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Fri, 4 May 2018 19:28:05 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r333260 - head/sys/arm/freescale/imx X-SVN-Group: head X-SVN-Commit-Author: ian X-SVN-Commit-Paths: head/sys/arm/freescale/imx X-SVN-Commit-Revision: 333260 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 May 2018 19:28:06 -0000 Author: ian Date: Fri May 4 19:28:05 2018 New Revision: 333260 URL: https://svnweb.freebsd.org/changeset/base/333260 Log: Properly support the GPIO_PIN_PRESET_{LOW,HIGH} options when configuring a gpio pin. If neither of the options is specified, pre-set the pin's output value to the pin's current input value, to achieve glitch-free transitions to output mode on pins that are pulled up or down at reset or via fdt pinctrl data. Modified: head/sys/arm/freescale/imx/imx_gpio.c Modified: head/sys/arm/freescale/imx/imx_gpio.c ============================================================================== --- head/sys/arm/freescale/imx/imx_gpio.c Fri May 4 18:59:01 2018 (r333259) +++ head/sys/arm/freescale/imx/imx_gpio.c Fri May 4 19:28:05 2018 (r333260) @@ -506,21 +506,41 @@ static void imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin, unsigned int flags) { - u_int newflags; + u_int newflags, pad; mtx_lock_spin(&sc->sc_mtx); /* - * Manage input/output; other flags not supported yet. + * Manage input/output; other flags not supported yet (maybe not ever, + * since we have no connection to the pad config registers from here). * + * When setting a pin to output, honor the PRESET_[LOW,HIGH] flags if + * present. Otherwise, for glitchless transistions on pins with pulls, + * read the current state of the pad and preset the DR register to drive + * the current value onto the pin before enabling the pin for output. + * * Note that changes to pin->gp_flags must be acccumulated in newflags * and stored with a single writeback to gp_flags at the end, to enable - * unlocked reads of that value elsewhere. + * unlocked reads of that value elsewhere. This is only about unlocked + * access to gp_flags from elsewhere; we still use locking in this + * function to protect r-m-w access to the hardware registers. */ if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) { newflags = pin->gp_flags & ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); if (flags & GPIO_PIN_OUTPUT) { + if (flags & GPIO_PIN_PRESET_LOW) { + pad = 0; + } else if (flags & GPIO_PIN_PRESET_HIGH) { + pad = 1; + } else { + if (flags & GPIO_PIN_OPENDRAIN) + pad = READ4(sc, IMX_GPIO_PSR_REG); + else + pad = READ4(sc, IMX_GPIO_DR_REG); + pad = (pad >> pin->gp_pin) & 1; + } newflags |= GPIO_PIN_OUTPUT; + SET4(sc, IMX_GPIO_DR_REG, (pad << pin->gp_pin)); SET4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); } else { newflags |= GPIO_PIN_INPUT; @@ -692,7 +712,7 @@ imx51_gpio_pin_access_32(device_t dev, uint32_t first_ sc = device_get_softc(dev); if (orig_pins != NULL) - *orig_pins = READ4(sc, IMX_GPIO_PSR_REG); + *orig_pins = READ4(sc, IMX_GPIO_DR_REG); if ((clear_pins | change_pins) != 0) { mtx_lock_spin(&sc->sc_mtx); @@ -718,7 +738,7 @@ imx51_gpio_pin_config_32(device_t dev, uint32_t first_ return (EINVAL); drclr = drset = oeclr = oeset = 0; - pads = READ4(sc, IMX_GPIO_PSR_REG); + pads = READ4(sc, IMX_GPIO_DR_REG); for (i = 0; i < num_pins; ++i) { bit = 1u << i;