From owner-freebsd-hackers Thu Feb 1 13:37:27 1996 Return-Path: owner-hackers Received: (from root@localhost) by freefall.freebsd.org (8.7.3/8.7.3) id NAA02210 for hackers-outgoing; Thu, 1 Feb 1996 13:37:27 -0800 (PST) Received: from phaeton.artisoft.com (phaeton.Artisoft.COM [198.17.250.211]) by freefall.freebsd.org (8.7.3/8.7.3) with SMTP id NAA02205 for ; Thu, 1 Feb 1996 13:37:22 -0800 (PST) Received: (from terry@localhost) by phaeton.artisoft.com (8.6.11/8.6.9) id OAA13787; Thu, 1 Feb 1996 14:29:25 -0700 From: Terry Lambert Message-Id: <199602012129.OAA13787@phaeton.artisoft.com> Subject: Re: Good news -- pipe stuff To: dfr@render.com (Doug Rabson) Date: Thu, 1 Feb 1996 14:29:25 -0700 (MST) Cc: hasty@rah.star-gate.com, lehey.pad@sni.de, tinguely@plains.nodak.edu, hackers@FreeBSD.ORG In-Reply-To: from "Doug Rabson" at Feb 1, 96 12:56:53 pm X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: owner-hackers@FreeBSD.ORG Precedence: bulk > Personally, I would prefer that Intel made byte and halfword memory > operations go as fast as 32bit operations. As far as I am concerned, the > two most useful pixel formats for 3D rendering are 8bit and 16bit. The > image quality gain for 32bit pixels is never enough to justify doubling > the memory bandwidth requirements. > > The first set of 3d hardware is a bit disappointing but its not too bad. > The second wave should be excellent. Intel's MMX instruction set > extensions make a P5 into a pretty good 3D accelerator too... I'd like to see unaligned acces of data cache items done with address space shift replication. That way I could do 32 bit I/O to the cache (re: Pentium bcopy) and not take a hit for unaligned source/target addresses. Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.