From owner-svn-src-head@FreeBSD.ORG Fri Apr 17 19:07:44 2009 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id A2BF4106564A; Fri, 17 Apr 2009 19:07:44 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 90F048FC0C; Fri, 17 Apr 2009 19:07:44 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n3HJ7ia4031859; Fri, 17 Apr 2009 19:07:44 GMT (envelope-from jhb@svn.freebsd.org) Received: (from jhb@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n3HJ7ilP031857; Fri, 17 Apr 2009 19:07:44 GMT (envelope-from jhb@svn.freebsd.org) Message-Id: <200904171907.n3HJ7ilP031857@svn.freebsd.org> From: John Baldwin Date: Fri, 17 Apr 2009 19:07:44 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r191222 - in head: sys/dev/pci usr.sbin/pciconf X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Apr 2009 19:07:45 -0000 Author: jhb Date: Fri Apr 17 19:07:44 2009 New Revision: 191222 URL: http://svn.freebsd.org/changeset/base/191222 Log: - Add a few more register defintions for the PCI express capability registers. - Cleanup PCI-X capability printf to not leave a dangling "supports" for some PCI-X bridges. - Display additional PCI express details including the negotiated and max link width and the actual and maximum supported max payload. MFC after: 1 month Modified: head/sys/dev/pci/pcireg.h head/usr.sbin/pciconf/cap.c Modified: head/sys/dev/pci/pcireg.h ============================================================================== --- head/sys/dev/pci/pcireg.h Fri Apr 17 18:48:50 2009 (r191221) +++ head/sys/dev/pci/pcireg.h Fri Apr 17 19:07:44 2009 (r191222) @@ -596,8 +596,36 @@ #define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050 #define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060 #define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070 +#define PCIM_EXP_TYPE_PCIE_BRIDGE 0x0080 +#define PCIM_EXP_TYPE_ROOT_INT_EP 0x0090 +#define PCIM_EXP_TYPE_ROOT_EC 0x00a0 #define PCIM_EXP_FLAGS_SLOT 0x0100 #define PCIM_EXP_FLAGS_IRQ 0x3e00 +#define PCIR_EXPRESS_DEVICE_CAP 0x4 +#define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007 +#define PCIR_EXPRESS_DEVICE_CTL 0x8 +#define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 +#define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 +#define PCIR_EXPRESS_DEVICE_STA 0xa +#define PCIR_EXPRESS_LINK_CAP 0xc +#define PCIM_LINK_CAP_MAX_SPEED 0x0000000f +#define PCIM_LINK_CAP_MAX_WIDTH 0x000003f0 +#define PCIM_LINK_CAP_ASPM 0x00000c00 +#define PCIM_LINK_CAP_L0S_EXIT 0x00007000 +#define PCIM_LINK_CAP_L1_EXIT 0x00038000 +#define PCIM_LINK_CAP_PORT 0xff000000 +#define PCIR_EXPRESS_LINK_CTL 0x10 +#define PCIR_EXPRESS_LINK_STA 0x12 +#define PCIM_LINK_STA_SPEED 0x000f +#define PCIM_LINK_STA_WIDTH 0x03f0 +#define PCIM_LINK_STA_TRAINING_ERROR 0x0400 +#define PCIM_LINK_STA_TRAINING 0x0800 +#define PCIM_LINK_STA_SLOT_CLOCK 0x1000 +#define PCIR_EXPRESS_SLOT_CAP 0x14 +#define PCIR_EXPRESS_SLOT_CTL 0x18 +#define PCIR_EXPRESS_SLOT_STA 0x1a +#define PCIR_EXPRESS_ROOT_CTL 0x1c +#define PCIR_EXPRESS_ROOT_STA 0x20 /* MSI-X definitions */ #define PCIR_MSIX_CTRL 0x2 Modified: head/usr.sbin/pciconf/cap.c ============================================================================== --- head/usr.sbin/pciconf/cap.c Fri Apr 17 18:48:50 2009 (r191221) +++ head/usr.sbin/pciconf/cap.c Fri Apr 17 19:07:44 2009 (r191222) @@ -151,7 +151,9 @@ cap_pcix(int fd, struct pci_conf *p, uin printf("64-bit "); if ((p->pc_hdr & PCIM_HDRTYPE) == 1) printf("bridge "); - printf("supports"); + if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP | + PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0) + printf("supports"); comma = 0; if (status & PCIXM_STATUS_133CAP) { printf("%s 133MHz", comma ? "," : ""); @@ -357,9 +359,12 @@ cap_subvendor(int fd, struct pci_conf *p printf("PCI Bridge card=0x%08x", id); } +#define MAX_PAYLOAD(field) (128 << (field)) + static void cap_express(int fd, struct pci_conf *p, uint8_t ptr) { + uint32_t val; uint16_t flags; flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_FLAGS, 2); @@ -383,12 +388,30 @@ cap_express(int fd, struct pci_conf *p, case PCIM_EXP_TYPE_PCI_BRIDGE: printf("PCI bridge"); break; + case PCIM_EXP_TYPE_PCIE_BRIDGE: + printf("PCI to PCIe bridge"); + break; + case PCIM_EXP_TYPE_ROOT_INT_EP: + printf("root endpoint"); + break; + case PCIM_EXP_TYPE_ROOT_EC: + printf("event collector"); + break; default: - printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 8); + printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 4); break; } if (flags & PCIM_EXP_FLAGS_IRQ) - printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 17); + printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 8); + val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CAP, 4); + flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CTL, 2); + printf(" max data %d(%d)", + MAX_PAYLOAD((flags & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5), + MAX_PAYLOAD(val & PCIM_EXP_CAP_MAX_PAYLOAD)); + val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_LINK_CAP, 4); + flags = read_config(fd, &p->pc_sel, ptr+ PCIR_EXPRESS_LINK_STA, 2); + printf(" link x%d(x%d)", (flags & PCIM_LINK_STA_WIDTH) >> 4, + (val & PCIM_LINK_CAP_MAX_WIDTH) >> 4); } static void