Date: Fri, 21 May 1999 09:24:32 +0100 (BST) From: Doug Rabson <dfr@nlsystems.com> To: Ladavac Marino <mladavac@metropolitan.at> Cc: "'Mike Smith'" <mike@smith.net.au>, Joel Ray Holveck <joelh@gnu.org>, Peter Wemm <peter@netplex.com.au>, Tommy Hallgren <thallgren@yahoo.com>, freebsd-hackers@FreeBSD.ORG Subject: RE: Lazy SPLs Message-ID: <Pine.BSF.4.05.9905210923210.509-100000@herring.nlsystems.com> In-Reply-To: <55586E7391ACD211B9730000C1100276179612@r-lmh-wi-100.corpnet.at>
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On Fri, 21 May 1999, Ladavac Marino wrote: > > -----Original Message----- > > From: Mike Smith [SMTP:mike@smith.net.au] > > Sent: Friday, May 21, 1999 2:16 AM > > To: Joel Ray Holveck > > Cc: Doug Rabson; Peter Wemm; Tommy Hallgren; > > freebsd-hackers@FreeBSD.ORG > > Subject: Re: Lazy SPLs > > > > > > > > Why mask out the interrupts at all, instead of queuing them in > > handler > > > level? > > > > Level-triggered interrupts are persistent conditions, not queueable > > events. They typically require device-driver level intervention to be > > > > cleared. This is a major error in the PCI design (no surprises > > there). > > > [ML] Whoa there! That's the MAJOR advantage of PCI design. > Open collector, active low, level triggered interrupts are the only > possibility for interupt line sharing without programmatically > accessible registers on card which say "yes, I am still interrupting". > > Active high, edge triggered interrupts are an abomination (there > is no way to reliably share the interrupt line and you cannot even wire > or it). They are the reason why one never has enough interrupt lines on > ISA. Interrupt sharing sucks. The processor should have more interrupt inputs. Modern alpha systems typically have as many interrupt inputs as there are pci slots * interrupt pins. -- Doug Rabson Mail: dfr@nlsystems.com Nonlinear Systems Ltd. Phone: +44 181 442 9037 To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message
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