From owner-svn-src-all@freebsd.org Wed Sep 18 07:22:38 2019 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id B5FBFF49E6; Wed, 18 Sep 2019 07:22:38 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 46YBJZ4RCJz3xgv; Wed, 18 Sep 2019 07:22:38 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 7B91C21979; Wed, 18 Sep 2019 07:22:38 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x8I7McT7005663; Wed, 18 Sep 2019 07:22:38 GMT (envelope-from jchandra@FreeBSD.org) Received: (from jchandra@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x8I7Mcjn005662; Wed, 18 Sep 2019 07:22:38 GMT (envelope-from jchandra@FreeBSD.org) Message-Id: <201909180722.x8I7Mcjn005662@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jchandra set sender to jchandra@FreeBSD.org using -f From: "Jayachandran C." Date: Wed, 18 Sep 2019 07:22:38 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r352473 - stable/12/sys/arm64/arm64 X-SVN-Group: stable-12 X-SVN-Commit-Author: jchandra X-SVN-Commit-Paths: stable/12/sys/arm64/arm64 X-SVN-Commit-Revision: 352473 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Sep 2019 07:22:38 -0000 Author: jchandra Date: Wed Sep 18 07:22:37 2019 New Revision: 352473 URL: https://svnweb.freebsd.org/changeset/base/352473 Log: MFC r340602: gitv3_its: fixes for multiple GIC ITS blocks First pass of support for multiple GIC ITS blocks with ACPI. Changes are to: * register the correct subset of interrupts with pic_register in case of ACPI. * initialize just the cpu interface for the first ITS, when domain information is not avialable. This has to be done until we split the per-CPU init to do LPI setup just once. * remove duplicate check for the GIC ITS domain, the sc_cpus are setup from domain, so the check again in per-CPU init seems unnecessary. Reviewed by: andrew Differential Revision: https://reviews.freebsd.org/D17841 Modified: stable/12/sys/arm64/arm64/gicv3_its.c Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/arm64/arm64/gicv3_its.c ============================================================================== --- stable/12/sys/arm64/arm64/gicv3_its.c Wed Sep 18 07:21:08 2019 (r352472) +++ stable/12/sys/arm64/arm64/gicv3_its.c Wed Sep 18 07:22:37 2019 (r352473) @@ -580,18 +580,11 @@ its_init_cpu(device_t dev, struct gicv3_its_softc *sc) uint64_t xbaser, tmp; uint32_t ctlr; u_int cpuid; - int domain; - if (!CPU_ISSET(PCPU_GET(cpuid), &sc->sc_cpus)) - return (0); - - if (bus_get_domain(dev, &domain) == 0) { - if (PCPU_GET(domain) != domain) - return (0); - } - gicv3 = device_get_parent(dev); cpuid = PCPU_GET(cpuid); + if (!CPU_ISSET(cpuid, &sc->sc_cpus)) + return (0); /* Check if the ITS is enabled on this CPU */ if ((gic_r_read_4(gicv3, GICR_TYPER) & GICR_TYPER_PLPIS) == 0) { @@ -729,12 +722,14 @@ gicv3_its_attach(device_t dev) /* Protects access to the ITS command circular buffer. */ mtx_init(&sc->sc_its_cmd_lock, "ITS cmd lock", NULL, MTX_SPIN); + CPU_ZERO(&sc->sc_cpus); if (bus_get_domain(dev, &domain) == 0) { - CPU_ZERO(&sc->sc_cpus); if (domain < MAXMEMDOM) CPU_COPY(&cpuset_domain[domain], &sc->sc_cpus); } else { - CPU_COPY(&all_cpus, &sc->sc_cpus); + /* XXX : cannot handle more than one ITS per cpu */ + if (device_get_unit(dev) == 0) + CPU_COPY(&all_cpus, &sc->sc_cpus); } /* Allocate the command circular buffer */ @@ -1737,7 +1732,7 @@ gicv3_its_acpi_attach(device_t dev) sc->sc_pic = intr_pic_register(dev, device_get_unit(dev) + ACPI_MSI_XREF); intr_pic_add_handler(device_get_parent(dev), sc->sc_pic, - gicv3_its_intr, sc, GIC_FIRST_LPI, LPI_NIRQS); + gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length); /* Register this device to handle MSI interrupts */ intr_msi_register(dev, device_get_unit(dev) + ACPI_MSI_XREF);