From owner-p4-projects@FreeBSD.ORG Thu Mar 6 12:48:41 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 3567D1065676; Thu, 6 Mar 2008 12:48:41 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id E8DBC1065672 for ; Thu, 6 Mar 2008 12:48:40 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id D756C8FC18 for ; Thu, 6 Mar 2008 12:48:40 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m26Cmenc093582 for ; Thu, 6 Mar 2008 12:48:40 GMT (envelope-from rrs@cisco.com) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m26Cmevh093580 for perforce@freebsd.org; Thu, 6 Mar 2008 12:48:40 GMT (envelope-from rrs@cisco.com) Date: Thu, 6 Mar 2008 12:48:40 GMT Message-Id: <200803061248.m26Cmevh093580@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to rrs@cisco.com using -f From: "Randall R. Stewart" To: Perforce Change Reviews Cc: Subject: PERFORCE change 136988 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Mar 2008 12:48:42 -0000 http://perforce.freebsd.org/chv.cgi?CH=136988 Change 136988 by rrs@rrs-mips2-jnpr on 2008/03/06 12:47:57 Move oct-state out of uart_device. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_dev_oct16550.c#19 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_dev_oct16550.c#19 (text+ko) ==== @@ -867,109 +867,3 @@ uart_unlock(sc->sc_hwmtx); return (0); } - -#ifdef DDB - -#define OCTEON_POW_WQ_INT_THR 0x8001670000000080ull -#define OCTEON_POW_WQ_INT_CNT 0x8001670000000100ull -#define OCTEON_POW_WQ_QOS_THR 0x8001670000000180ull -#define OCTEON_POW_WQ_INT 0x8001670000000200ull -#define OCTEON_POW_WQ_INT_PC 0x8001670000000208ull - -void db_dump_intr_state(void); - -void -db_dump_intr_state(void) -{ - uint32_t status_bits; - uint64_t ciu_intr_reg_addr; - uint64_t regstate1, regstate2; - int i; - status_bits = mips_rd_status(); - printf("Mips SR is currently %x\n", status_bits); - - - printf("Core Interrupt summary's IP2/IP3\n"); - ciu_intr_reg_addr = OCTEON_CIU_SUMMARY_BASE_ADDR; - for(i=0; i<16; i++) { - regstate1 = oct_read64(ciu_intr_reg_addr); - regstate2 = oct_read64(ciu_intr_reg_addr + 0x8); - printf("Core:%d Reg:%llx IP2:%llx IP3:%llx\n", - i, ciu_intr_reg_addr, regstate1, regstate2); - /* next register set please */ - ciu_intr_reg_addr += 0x10; - } - printf("Core Interrupt enable 0 IP2/IP3\n"); - ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR; - for(i=0; i<16; i++) { - regstate1 = oct_read64(ciu_intr_reg_addr); - regstate2 = oct_read64(ciu_intr_reg_addr + 0x10); - printf("Core:%d Reg:%llx IP2:%llx IP3:%llx\n", - i, ciu_intr_reg_addr, regstate1, regstate2); - /* next register set please */ - ciu_intr_reg_addr += 0x10; - } - printf("Core Interrupt enable 1 IP2/IP3\n"); - ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR + 0x8; - for(i=0; i<16; i++) { - regstate1 = oct_read64(ciu_intr_reg_addr); - regstate2 = oct_read64(ciu_intr_reg_addr + 0x10); - printf("Core:%d Reg:%llx IP2:%llx IP3:%llx\n", - i, ciu_intr_reg_addr, regstate1, regstate2); - /* next register set please */ - ciu_intr_reg_addr += 0x10; - } - ciu_intr_reg_addr = OCTEON_POW_WQ_INT_THR; - printf("Pow Threshold registers\n"); - for(i=0; i<16; i++) { - regstate1 = oct_read64(ciu_intr_reg_addr); - printf("%llx tc:%llx tc_thr:%llx ds_thr:%llx iq_thr:%llx\n", - ciu_intr_reg_addr, - ((regstate1 >> 28) & 0x00001) , - ((regstate1 >> 24) & 0x0000f), - ((regstate1 >> 12) & 0x003ff), - (regstate1 & 0x003ff)); - ciu_intr_reg_addr += 0x8; - } - ciu_intr_reg_addr = OCTEON_POW_WQ_INT_CNT; - printf("Pow int cnt registers\n"); - for(i=0; i<16; i++) { - regstate1 = oct_read64(ciu_intr_reg_addr); - printf("%llx tc_cnt:%llx ds_cnt:%llx iq_cnt:%llx\n", - ciu_intr_reg_addr, - ((regstate1 >> 24) & 0x0000f), - ((regstate1 >> 12) & 0x003ff), - (regstate1 & 0x003ff)); - ciu_intr_reg_addr += 0x8; - } - - ciu_intr_reg_addr = OCTEON_POW_WQ_QOS_THR; - printf("Pow QOS thr registers\n"); - for(i=0; i<16; i++) { - regstate1 = oct_read64(ciu_intr_reg_addr); - printf("%llx des_cnt:%llx buf_cnt:%llx free_cnt:%llx max_thr:%llx min_thr:%llx\n", - ciu_intr_reg_addr, - ((regstate1 >> 48) & 0x00fff), - ((regstate1 >> 36) & 0x00fff), - ((regstate1 >> 24) & 0x00fff), - ((regstate1 >> 12) & 0x003ff), - (regstate1 & 0x003ff)); - ciu_intr_reg_addr += 0x8; - } - ciu_intr_reg_addr = OCTEON_POW_WQ_INT; - regstate1 = oct_read64(ciu_intr_reg_addr); - printf("POW_WQ_INT:%llx val:%llx\n", ciu_intr_reg_addr, regstate1); - ciu_intr_reg_addr = OCTEON_POW_WQ_INT_PC; - regstate1 = oct_read64(ciu_intr_reg_addr); - printf("POW_WQ_INT_PC:%llx val:%llx\n", ciu_intr_reg_addr, regstate1); -} - -#include -#include - -DB_SHOW_COMMAND(oct_state, ddb_dump_intr_state) -{ - db_dump_intr_state(); -} - -#endif