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From: "matthew c. mead" <mmead@Glock.COM>
Message-Id: <199605141518.LAA08531@Glock.COM>
Subject: Re: Triton chipset with 256k cache caches 32M only?
To: davidg@Root.COM
Date: Tue, 14 May 1996 11:18:14 -0400 (EDT)
Cc: joerg_wunsch@uriah.heep.sax.de, blh@nol.net, jgreco@brasil.moneng.mei.com,
        hackers@freebsd.org, hardware@freebsd.org
In-Reply-To: <199605141514.IAA12912@Root.COM> from "David Greenman" at May 14, 96 08:14:38 am
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David Greenman writes:

> > I'd really like to do ECC, I just don't have the money for
> >it right now.  So does this ECC work the same as the ECC
> >on DEC Alphas?  On the Alphas, you put in 5M for every 4M
> >of addressable ram.  Is there a fifth simm slot on these
> >motherboards where a non ECC capable motherboard would have 4?

>    No, it uses the parity bits. Only 8 syndrome bits are needed
> for 64bit words.

	Hmm.  So does that mean the ECC is limited to single (odd
number of) bit errors?



-matt

-- 
Matthew C. Mead

mmead@Glock.COM
http://www.Glock.COM/~mmead/