From owner-svn-src-head@FreeBSD.ORG Sat Apr 26 20:03:05 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id E909FC8D; Sat, 26 Apr 2014 20:03:04 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id D580C1081; Sat, 26 Apr 2014 20:03:04 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s3QK34cG023301; Sat, 26 Apr 2014 20:03:04 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s3QK34gj023300; Sat, 26 Apr 2014 20:03:04 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201404262003.s3QK34gj023300@svn.freebsd.org> From: Ian Lepore Date: Sat, 26 Apr 2014 20:03:04 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r264983 - head/sys/dev/uart X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 26 Apr 2014 20:03:05 -0000 Author: ian Date: Sat Apr 26 20:03:04 2014 New Revision: 264983 URL: http://svnweb.freebsd.org/changeset/base/264983 Log: Flesh out imx_uart_init() so that we're not relying on u-boot to init the hardware (meaning uarts other than the console will work). Modified: head/sys/dev/uart/uart_dev_imx.c Modified: head/sys/dev/uart/uart_dev_imx.c ============================================================================== --- head/sys/dev/uart/uart_dev_imx.c Sat Apr 26 19:30:04 2014 (r264982) +++ head/sys/dev/uart/uart_dev_imx.c Sat Apr 26 20:03:04 2014 (r264983) @@ -43,10 +43,11 @@ __FBSDID("$FreeBSD$"); #include #include #include - #include - #include "uart_if.h" + +#include + /* * Low-level UART interface. */ @@ -66,6 +67,22 @@ static struct uart_ops uart_imx_uart_ops .getc = imx_uart_getc, }; +#if 0 /* Handy when debugging. */ +static void +dumpregs(struct uart_bas *bas, const char * msg) +{ + + if (!bootverbose) + return; + printf("%s bsh 0x%08lx UCR1 0x%08x UCR2 0x%08x " + "UCR3 0x%08x UCR4 0x%08x USR1 0x%08x USR2 0x%08x\n", + msg, bas->bsh, + GETREG(bas, REG(UCR1)), GETREG(bas, REG(UCR2)), + GETREG(bas, REG(UCR3)), GETREG(bas, REG(UCR4)), + GETREG(bas, REG(USR1)), GETREG(bas, REG(USR2))); +} +#endif + static int imx_uart_probe(struct uart_bas *bas) { @@ -77,7 +94,59 @@ static void imx_uart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, int parity) { + uint32_t baseclk, reg; + + /* Enable the device and the RX/TX channels. */ + SET(bas, REG(UCR1), FLD(UCR1, UARTEN)); + SET(bas, REG(UCR2), FLD(UCR2, RXEN) | FLD(UCR2, TXEN)); + + if (databits == 7) + DIS(bas, UCR2, WS); + else + ENA(bas, UCR2, WS); + + if (stopbits == 2) + ENA(bas, UCR2, STPB); + else + DIS(bas, UCR2, STPB); + + switch (parity) { + case UART_PARITY_ODD: + DIS(bas, UCR2, PROE); + ENA(bas, UCR2, PREN); + break; + case UART_PARITY_EVEN: + ENA(bas, UCR2, PROE); + ENA(bas, UCR2, PREN); + break; + case UART_PARITY_MARK: + case UART_PARITY_SPACE: + /* FALLTHROUGH: Hardware doesn't support mark/space. */ + case UART_PARITY_NONE: + default: + DIS(bas, UCR2, PREN); + break; + } + /* + * The hardware has an extremely flexible baud clock: it allows setting + * both the numerator and denominator of the divider, as well as a + * separate pre-divider. We simplify that problem by assuming a + * pre-divider and numerator of one because our base clock is so fast we + * can reach virtually any reasonable speed with a simple divisor. The + * numerator value actually includes the 16x over-sampling; the register + * value is the numerator-1, so we have a hard-coded 15. Note that a + * quirk of the hardware requires that both UBIR and UBMR be set back to + * back in order for the change to take effect. + */ + if (baudrate > 0) { + baseclk = imx_ccm_uart_hz(); + reg = GETREG(bas, REG(UFCR)); + reg = (reg & ~IMXUART_UFCR_RFDIV_MASK) | IMXUART_UFCR_RFDIV_DIV1; + SETREG(bas, REG(UFCR), reg); + SETREG(bas, REG(UBIR), 15); + SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1); + } } static void @@ -218,6 +287,8 @@ imx_uart_bus_attach(struct uart_softc *s DIS(bas, UCR3, RI); DIS(bas, UCR3, DCD); DIS(bas, UCR3, DTRDEN); + ENA(bas, UCR2, IRTS); + ENA(bas, UCR3, RXDMUXSEL); /* ACK all interrupts */ SETREG(bas, REG(USR1), 0xffff);