Date: Tue, 12 Jun 2012 08:51:34 -0600 From: Ian Lepore <freebsd@damnhippie.dyndns.org> To: Wojciech Puchar <wojtek@wojtek.tensor.gdynia.pl> Cc: Konstantin Belousov <kostikbel@gmail.com>, freebsd-hackers@freebsd.org Subject: Re: wired memory - again! Message-ID: <1339512694.36051.362.camel@revolution.hippie.lan> In-Reply-To: <alpine.BSF.2.00.1206092244550.9248@wojtek.tensor.gdynia.pl> References: <alpine.BSF.2.00.1206090920030.84632@wojtek.tensor.gdynia.pl> <1339259223.36051.328.camel@revolution.hippie.lan> <20120609165217.GO85127@deviant.kiev.zoral.com.ua> <alpine.BSF.2.00.1206092244550.9248@wojtek.tensor.gdynia.pl>
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On Sat, 2012-06-09 at 22:45 +0200, Wojciech Puchar wrote: > > > > First, all memory allocated by UMA and consequently malloc(9) is > > wired. In other words, almost all memory used by kernel is accounted > > as wired. > > > yes i understand this. still i found no way how to find out what allocated > that much. > > > > Second, the buffer cache wires the pages which are inserted into VMIO > > buffers. So your observation is basically right, cached buffers means > > what are exactly "VMIO" buffers. i understand that page must be wired WHEN > doing I/O. > But i have too much wired memory even when doing no I/O at all. I agree, this is The Big Question for me. Why does the system keep wired writable mappings of the buffers in kva after the IO operations are completed? If it did not do so, it would fix the instruction-cache-disabled bug that kills performance on VIVT cache architectures (arm and mips) and it would reduce the amount of wired memory (that apparently doesn't need to be wired, unless I've missed the implications of a previous reply in this thread). -- Ian
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