From owner-freebsd-ppc@freebsd.org Tue Apr 23 04:57:38 2019 Return-Path: Delivered-To: freebsd-ppc@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 93133158E5C5 for ; Tue, 23 Apr 2019 04:57:38 +0000 (UTC) (envelope-from marklmi@yahoo.com) Received: from sonic312-25.consmr.mail.gq1.yahoo.com (sonic312-25.consmr.mail.gq1.yahoo.com [98.137.69.206]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 615308F267 for ; Tue, 23 Apr 2019 04:57:37 +0000 (UTC) (envelope-from marklmi@yahoo.com) X-YMail-OSG: 0XIPNWYVM1kF_RcGj5luuZqbv6wlLghhr3axKB2tOiTHlG7lYutNKUBKNNk2k7Y wBD7fUb.OPGZuj6g.LCH8cMwFNmAygjsx4rTiiJTOI4hRJeVaFbdRbIH00p0eVNMlY6jOPLvae3F HpIsJ6jwe1BCUt_QVrvRLkz1ZgiGnqqoEmy.FIrq0MU0FTiCU9jm2cqRzXf2CJRMyDDMBDFuWsa7 ck50cwAaiFClyiEoAzp8VR6ilatmhR6NfxHlbZc6cSVTWswesC0E5CYEUrLEui8ogKDgvbesVVcN aD6a.EFJQNCrhfKsgq5UxAKjNWz14bLav7dVH6Ulxn8j8lSXckCgrm6fH31CMp1jHX68qQtOWkeO aU6XFVWJuDherEy66MX1DTb7FEsgN5O_k4eJ8H0UF796zC8c2nWyn0Zkol_9L9aagv4ILj9ZzKgm G9sCnMWY_SyNmwcDdVuMnTRttwzAOAvY4nepEUs_V5w2StNRn4Tb2X9NLKqq3dLnjqFzLnmSn7RP h4lUgxxWL8KkZLujahYrpbC0oMxTJnOKvTGKNHbdIAGeQY_6FgBt5aRfN872ySSQK3fCv_Q0AoOa 4Bm4FnUSZHehsYpgb6GVl0VXouFrRnY6m7c7WCdwbeXngi_1C0z3fHwgpz41mtrY7QK9AtxzlsWu yJFVMYsH7KnOxDDAYOKypMVPorNK64bQZl_VOlH3mdkVawk96M7Lb2Voa4xj7_qCVf.ceUXdAGFC HRQbp.uqJgvxd.HDbmch2TnH6zj0WRck2E.4CNfzJv4x6QaUAeRabPO4wfjSjP.zgIP06od3lPfc 5TOcrh85JcjppixaDPf._gdh493h4p8Q0s9h1LxTHjHJHt1THTNEyPGFK2xxT1jLk6o4sCUcJlpr .kH4sXJI6Yj_hQXzt3A3GRqgpIxp0s8nrw2qiau3UPV6qHVvh.fbzt6wz2ZAXsdxXhdrnB5TGRmx o0WcUNy6_emdld1Zh15kVZkr.gyMBtkDEQDhH7SavCLieVNluoGcRHQugCVCKnloQbZd5o2sBBDc MFRqVaOUP9rm_pkK484BHDQwpE3uI8CZpkRb0kLPsbI7zsARsb1G2zeZwwggDgZNFw1ikBmTlqjR U.vB9oeANWmL_q2gLMli6_PPa_g-- Received: from sonic.gate.mail.ne1.yahoo.com by sonic312.consmr.mail.gq1.yahoo.com with HTTP; Tue, 23 Apr 2019 04:57:30 +0000 Received: from c-76-115-7-162.hsd1.or.comcast.net (EHLO [192.168.1.103]) ([76.115.7.162]) by smtp429.mail.gq1.yahoo.com (Oath Hermes SMTP Server) with ESMTPA ID 3b17d49df55c7e76aa8d4f1b0efd7ec9; Tue, 23 Apr 2019 04:57:27 +0000 (UTC) From: Mark Millard Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Mime-Version: 1.0 (Mac OS X Mail 12.4 \(3445.104.8\)) Subject: Re: MPC750 (iMac G3) and disabling interrupts: sync after mtsr required according to the manual (at least isync in places?) Date: Mon, 22 Apr 2019 21:57:26 -0700 References: <52A9F96F-3615-44C9-BA2B-355EDAA4A1AF@yahoo.com> To: FreeBSD PowerPC ML , Justin Hibbits In-Reply-To: <52A9F96F-3615-44C9-BA2B-355EDAA4A1AF@yahoo.com> Message-Id: <6CB8FC2D-1D6D-4797-9D9B-F905A831AF3B@yahoo.com> X-Mailer: Apple Mail (2.3445.104.8) X-Rspamd-Queue-Id: 615308F267 X-Spamd-Bar: - X-Spamd-Result: default: False [-1.60 / 15.00]; RCVD_VIA_SMTP_AUTH(0.00)[]; R_SPF_ALLOW(-0.20)[+ptr:yahoo.com]; MV_CASE(0.50)[]; FREEMAIL_FROM(0.00)[yahoo.com]; RCVD_COUNT_THREE(0.00)[3]; TO_DN_ALL(0.00)[]; DKIM_TRACE(0.00)[yahoo.com:+]; MX_GOOD(-0.01)[cached: mta6.am0.yahoodns.net]; RCPT_COUNT_TWO(0.00)[2]; DMARC_POLICY_ALLOW(-0.50)[yahoo.com,reject]; FROM_EQ_ENVFROM(0.00)[]; IP_SCORE(0.31)[ipnet: 98.137.64.0/21(0.91), asn: 36647(0.73), country: US(-0.06)]; MIME_TRACE(0.00)[0:+]; FREEMAIL_ENVFROM(0.00)[yahoo.com]; ASN(0.00)[asn:36647, ipnet:98.137.64.0/21, country:US]; MID_RHS_MATCH_FROM(0.00)[]; SUBJECT_HAS_QUESTION(0.00)[]; ARC_NA(0.00)[]; NEURAL_HAM_MEDIUM(-0.99)[-0.991,0]; R_DKIM_ALLOW(-0.20)[yahoo.com:s=s2048]; FROM_HAS_DN(0.00)[]; DWL_DNSWL_NONE(0.00)[yahoo.com.dwl.dnswl.org : 127.0.5.0]; NEURAL_SPAM_SHORT(0.57)[0.571,0]; NEURAL_HAM_LONG(-0.98)[-0.984,0]; MIME_GOOD(-0.10)[text/plain]; RCVD_TLS_LAST(0.00)[]; TO_MATCH_ENVRCPT_SOME(0.00)[]; RCVD_IN_DNSWL_NONE(0.00)[206.69.137.98.list.dnswl.org : 127.0.5.0] X-BeenThere: freebsd-ppc@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Porting FreeBSD to the PowerPC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 Apr 2019 04:57:38 -0000 On 2019-Apr-22, at 15:27, Mark Millard wrote: > The below was prompted by observed iMac G3 behavior > with modern FreeBSD, so MPC750 behavior. > > First I list the most worrisome code that I noticed, > before the more general background of which the > below is an example. > > For the 32-bit aim code: > > CNAME(trapexit): > > /* Disable interrupts: */ > mfmsr %r3 > andi. %r3,%r3,~PSL_EE@l > mtmsr %r3 > /* Test AST pending: */ > lwz %r5,FRAME_SRR1+8(%r1) > mtcr %r5 > bf 17,1f /* branch if PSL_PR is false */ > > GET_CPUINFO(%r3) /* get per-CPU pointer */ > > Note: the 64-bit code has an isync before the > "Test AST pending" code. (No sync.) So far the following seems to have changed the MPC750 based iMac G3 from getting a mix of Machine Checks vs. Data Storage Interrupts for the same places in the code, to getting just Data Storage Interrupts for those places: Index: /usr/src/sys/powerpc/aim/trap_subr32.S =================================================================== --- /usr/src/sys/powerpc/aim/trap_subr32.S (revision 345758) +++ /usr/src/sys/powerpc/aim/trap_subr32.S (working copy) @@ -68,7 +68,7 @@ lwzu sr,PM_SR(pmap); \ RESTORE_SRS(pmap,sr) \ /* Restore SR 12 */ \ - lwz sr,12*4(pmap); mtsr 12,sr + lwz sr,12*4(pmap); mtsr 12,sr; isync /* * Kernel SRs are loaded directly from kernel_pmap_ @@ -799,6 +799,7 @@ mfmsr %r3 andi. %r3,%r3,~PSL_EE@l mtmsr %r3 + isync /* Test AST pending: */ lwz %r5,FRAME_SRR1+8(%r1) mtcr %r5 The MPC750 requires isync after mtsr (or mtsrin) and the one for "12,sr" is off by itself instead of being in the middle of the main sequence of mtsr's (which have a following isync). [While the above may be necessary, it is far from sufficient for making the MPC750 operate with active, competing processes/threads. (boot -s operates longer if one keeps things simple.) But I did not intend for the list-submittal to be for getting the MPC750 context working well overall.] > The below gets into why that 32-bit code (and > possibly more) is a worry: lack of sync (or at > least isync) after using mtmsr to disable > interrupts. > > > https://www.nxp.com/docs/en/reference-manual/MPC750UM.pdf > reports that a sync after the mtmsr is required for disabling > interrupts fully before whatever follows. (The example also > disables ME, FE0, and FE1, intended to be used before explicitly > loading the cache in contexts where all 4 forms of exceptions > are a worry.) > > It also has wording that mtmsr "does not ensure subsequent > instructions execute in the newly established environment". > > A similar example is made relative to sync after setting MSR[IR] > and/or MSR[DR]. It mentions isync instead of sync relative to > MSR[PR] via mtmsr. I'll ignore MSR[PR] below. > > (The MPC750 seems to have just one sync instruction with > one official encoding, no lwsync or other such variants > with alternate field values in the encoding.) > > > As for the code generally . . . > > powerpc64 and 32-bit powerpc FreeBSD currently have: > > static __inline register_t > intr_disable(void) > { > register_t msr; > > msr = mfmsr(); > mtmsr(msr & ~PSL_EE); > return (msr); > } > > where: > > static __inline void > mtmsr(register_t value) > { > > __asm __volatile ("mtmsr %0; isync" :: "r"(value)); > } > > (So there is an implicit isync in mtmsr(...) use.) > > There are lots of places using PSL_EE to disable interrupts > without calling intr_disable --but they still use mtmsr(...) > [other than assembler contexts]. > > For things that are involved on the MPC750, I'm mostly > worried about examples that have neither sync nor isync, > secondarily about not having sync. (I note some > other points as well.) > > > Relative to PDL_EE: > > powerpc_init has a disable with no sync. > cpu_est_clockrate seem to use a DELAY(1000) for > the MPC750 (and some others). But other settings > are also involved. cpu_dep_bootstrap has no sync. > (Not that cpu_dep_bootstrap is likely to be used > with MPC750s, certainly not with iMac G3s.) > > aim's trapexit for 32-bit has no sync or isync > for its disable but 64-bit has just isync. 32-bit > has just isync for the enable. FRAME_LEAVE uses > only isync (32-bit and 64-bit). breakpoint (32-bit > and 64-bit) uses only isync. (Assembler contexts.) > > write_scom uses isync. read_scom uses isync. pcr_set > uses isync. (So double isync's(?), one from mtmsr(...) > use?) > > flush_disable_caches uses a following powerpc_sync(); > isync() sequence. (Again a double isync(?): isync; > sync; isync; sequence?) > > > Relative to PSL_IR and PSL_DR: > > aim_early_init has an example of no use of sync > when ofwentry==0. aim_cpu_init has an example of no use > of sync. moea_bootstrap has 2 examples of no use of > sync. > > FRAME_SETUP uses just isync. FRAME_LEAVE uses just isync > (but also has a PSL_ME involved). Both 32-bit and 64-bit > for those. cpu_wakeup_handler (64-bit) uses just isync. > (Assembler contexts.) > > flush_disable_caches has sync and isync after a PDL_DR > use. (Again a double isync(?): isync; sync; isync; > sequence?) [PSL_DR is mixed with PSL_EE. as I remember.] > === Mark Millard marklmi at yahoo.com ( dsl-only.net went away in early 2018-Mar)