From owner-svn-src-all@freebsd.org Thu Feb 11 12:01:35 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 335BCAA5A87; Thu, 11 Feb 2016 12:01:35 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 05964D7E; Thu, 11 Feb 2016 12:01:34 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u1BC1YGZ050536; Thu, 11 Feb 2016 12:01:34 GMT (envelope-from zbb@FreeBSD.org) Received: (from zbb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u1BC1XXv050534; Thu, 11 Feb 2016 12:01:33 GMT (envelope-from zbb@FreeBSD.org) Message-Id: <201602111201.u1BC1XXv050534@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: zbb set sender to zbb@FreeBSD.org using -f From: Zbigniew Bodek Date: Thu, 11 Feb 2016 12:01:33 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r295517 - head/sys/arm64/arm64 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Feb 2016 12:01:35 -0000 Author: zbb Date: Thu Feb 11 12:01:33 2016 New Revision: 295517 URL: https://svnweb.freebsd.org/changeset/base/295517 Log: Initially bind all interrupts to the boot CPU when using GICv3 This should be done by routing all interrupts to CPU0, different assignment will be induced by either interrupts shuffling or bus_bind_intr(). Reviewed by: wma Obtained from: Semihalf Sponsored by: Cavium Differential Revision: https://reviews.freebsd.org/D5229 Modified: head/sys/arm64/arm64/gic_v3.c head/sys/arm64/arm64/gic_v3_its.c Modified: head/sys/arm64/arm64/gic_v3.c ============================================================================== --- head/sys/arm64/arm64/gic_v3.c Thu Feb 11 11:59:32 2016 (r295516) +++ head/sys/arm64/arm64/gic_v3.c Thu Feb 11 12:01:33 2016 (r295517) @@ -565,7 +565,7 @@ gic_v3_dist_init(struct gic_v3_softc *sc /* * 4. Route all interrupts to boot CPU. */ - aff = CPU_AFFINITY(PCPU_GET(cpuid)); + aff = CPU_AFFINITY(0); for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i++) gic_d_write(sc, 4, GICD_IROUTER(i), aff); Modified: head/sys/arm64/arm64/gic_v3_its.c ============================================================================== --- head/sys/arm64/arm64/gic_v3_its.c Thu Feb 11 11:59:32 2016 (r295516) +++ head/sys/arm64/arm64/gic_v3_its.c Thu Feb 11 12:01:33 2016 (r295517) @@ -1430,10 +1430,10 @@ its_device_alloc_locked(struct gic_v3_it } /* - * XXX ARM64TODO: Currently all interrupts are going - * to be bound to the CPU that performs the configuration. + * Initially all interrupts go to CPU0 but can be moved + * to another CPU by bus_bind_intr() or interrupts shuffling. */ - cpuid = PCPU_GET(cpuid); + cpuid = 0; newdev->col = sc->its_cols[cpuid]; TAILQ_INSERT_TAIL(&sc->its_dev_list, newdev, entry);