From owner-svn-src-head@FreeBSD.ORG Sat Dec 3 13:51:57 2011 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id EF841106566C; Sat, 3 Dec 2011 13:51:57 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id DF4918FC0C; Sat, 3 Dec 2011 13:51:57 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id pB3Dpv9l041817; Sat, 3 Dec 2011 13:51:57 GMT (envelope-from marius@svn.freebsd.org) Received: (from marius@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id pB3DpvpU041815; Sat, 3 Dec 2011 13:51:57 GMT (envelope-from marius@svn.freebsd.org) Message-Id: <201112031351.pB3DpvpU041815@svn.freebsd.org> From: Marius Strobl Date: Sat, 3 Dec 2011 13:51:57 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r228222 - head/sys/sparc64/include X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 03 Dec 2011 13:51:58 -0000 Author: marius Date: Sat Dec 3 13:51:57 2011 New Revision: 228222 URL: http://svn.freebsd.org/changeset/base/228222 Log: Revert r225889 a bit. While it's correct that in total store order there's no need to additionally add CPU memory barriers to the acquire variants of atomic(9), these are documented to also include compiler memory barriers. So add the latter, which were previously included by using membar(), back. Modified: head/sys/sparc64/include/atomic.h Modified: head/sys/sparc64/include/atomic.h ============================================================================== --- head/sys/sparc64/include/atomic.h Sat Dec 3 12:35:13 2011 (r228221) +++ head/sys/sparc64/include/atomic.h Sat Dec 3 13:51:57 2011 (r228222) @@ -78,7 +78,7 @@ * order which we use for running the kernel and all of the userland atomic * loads and stores behave as if the were followed by a membar with a mask * of #LoadLoad | #LoadStore | #StoreStore. In order to be also sufficient - * for use of relaxed memory ordering, the atomic_cas() in the acq variants + * for use of relaxed memory ordering, the atomic_cas() in the acq variants * additionally would have to be followed by a membar #LoadLoad | #LoadStore. * Due to the suggested assembly syntax of the membar operands containing a * # character, they cannot be used in macros. The cmask and mmask bits thus @@ -97,6 +97,7 @@ #define atomic_cas_acq(p, e, s, sz) ({ \ itype(sz) v; \ v = atomic_cas((p), (e), (s), sz); \ + __asm __volatile("" : : : "memory"); \ v; \ }) @@ -121,6 +122,7 @@ #define atomic_op_acq(p, op, v, sz) ({ \ itype(sz) t; \ t = atomic_op((p), op, (v), sz); \ + __asm __volatile("" : : : "memory"); \ t; \ }) @@ -137,6 +139,7 @@ #define atomic_load_acq(p, sz) ({ \ itype(sz) v; \ v = atomic_load((p), sz); \ + __asm __volatile("" : : : "memory"); \ v; \ })