From nobody Wed Sep 28 10:18:12 2022 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4Mcsrh3bMMz4dWCn; Wed, 28 Sep 2022 10:18:12 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Mcsrh34mJz3GT8; Wed, 28 Sep 2022 10:18:12 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1664360292; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=h5nyf+EKkMm9IYn+TvUlyDh9dN7q1nUPdnDXgi4IPFc=; b=e6vU0gvpp38yfI38NIAYdmPwmGLHHcXVtlQ9sjFUlTmeEuvJlzanjUJQyqVMjCQxJU8vMH 7g7BfNclKfvjMChGVttz+abi87v1QzRdnA2GvkhbFxvUKKGoLoT6raaC6ilZUfvV5TQnzh juUpTWfEsvChCqealFSO25RJdnh4jPaoiyTuOBD4T3RBKupSZ9ccmJZpJJnldvLFerz7Gm qZazHdF00BsAY/fWd1hR/mwPDbvbLhth0czEuXExVulpVuSaaWyla3wp40WekJ/G+kyvIJ e6Nn2nVhZGcyp/kRQmpIXPggD29xQNBi+egJ3LxIcGIBuBXrahxJcBAkTQBY7w== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4Mcsrh27NvzRFL; Wed, 28 Sep 2022 10:18:12 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 28SAICW4029222; Wed, 28 Sep 2022 10:18:12 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 28SAIC6Q029221; Wed, 28 Sep 2022 10:18:12 GMT (envelope-from git) Date: Wed, 28 Sep 2022 10:18:12 GMT Message-Id: <202209281018.28SAIC6Q029221@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: a42206a7ca77 - main - Reduce the arm64 ID registers we print List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: a42206a7ca773fafad396cd89f77f3a369a75a17 Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1664360292; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=h5nyf+EKkMm9IYn+TvUlyDh9dN7q1nUPdnDXgi4IPFc=; b=Lu97tL6gSz8UEV/+IpKA7HAHqPRP6vTZ3gD64dwpx3dgifsMDLL0Bi0UW1vBjGEAnclJnH r8IvkBUep53m0sMmxdQARuUR77Ed1uxN6HM7MJRuyneOe8ID1LaTG7i0gwSUU+JGzJ1Q75 cJiddz7aTFipb4UI5XWfOhX1IdRYLPQrkE+fNHMYMz4iFW+LHaSx+LYjOUU6ICTli03gKK eWKn9AzXikzCBD3NiFMB8gTiP8NpMASmmakTHXU24DqkUiOIo4aB56blw/d8lZs5oVBCp9 QdAHfh5xcXh1DS4UT158xd3zFQxpuXpWy6u4QHQ/soQ3rI/VhmqXWh5SIUqd9g== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1664360292; a=rsa-sha256; cv=none; b=XN9uDX+XvjVpmicD5TdgXCcI2YuOz8sctO/68uFUd9GHXRExFGu/iJss7BWpxmun8IGYeD XpwMlG8DxJgv78BZqjlsHV9iHWMKNKhHdaa8vgCeN4hUxATUylKX1CGpY/LT2mLEJbICBm NOG5Ku3y9ewwbygWwOekUv61shrAXL1Z22vgQwgx3pxWNCm+z10BEWpWYsEJhXKyzDjBva t4Qcv8JCtuBz4rgV7srFjVn1pln7f2ydr6EnbvT2KQ+dPQ0/io8ChkRaPAo02wp/XDzq3a gQ1PSe3YfUbSPWda+/TNTGUYb+gPYMM461aXhlhNhLR4MZ+pZJJIdSHM5eXo8Q== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=a42206a7ca773fafad396cd89f77f3a369a75a17 commit a42206a7ca773fafad396cd89f77f3a369a75a17 Author: Andrew Turner AuthorDate: 2022-07-19 08:47:23 +0000 Commit: Andrew Turner CommitDate: 2022-09-28 09:53:00 +0000 Reduce the arm64 ID registers we print On systems with different CPUs we may print all the ID registers for all CPUs. Reduce this to just print them when they change from the previous CPU. Sponsored by: The FreeBSD Foundation --- sys/arm64/arm64/identcpu.c | 117 +++++++++++---------------------------------- 1 file changed, 27 insertions(+), 90 deletions(-) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index 24b1bd0b1dfd..b1fead21acee 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -148,26 +148,6 @@ struct cpu_desc { static struct cpu_desc cpu_desc[MAXCPU]; static struct cpu_desc kern_cpu_desc; static struct cpu_desc user_cpu_desc; -static u_int cpu_print_regs; -#define PRINT_ID_AA64_AFR0 0x00000001 -#define PRINT_ID_AA64_AFR1 0x00000002 -#define PRINT_ID_AA64_DFR0 0x00000010 -#define PRINT_ID_AA64_DFR1 0x00000020 -#define PRINT_ID_AA64_ISAR0 0x00000100 -#define PRINT_ID_AA64_ISAR1 0x00000200 -#define PRINT_ID_AA64_ISAR2 0x00000400 -#define PRINT_ID_AA64_MMFR0 0x00001000 -#define PRINT_ID_AA64_MMFR1 0x00002000 -#define PRINT_ID_AA64_MMFR2 0x00004000 -#define PRINT_ID_AA64_PFR0 0x00010000 -#define PRINT_ID_AA64_PFR1 0x00020000 -#define PRINT_ID_AA64_ZFR0 0x00100000 -#ifdef COMPAT_FREEBSD32 -#define PRINT_ID_ISAR5 0x01000000 -#define PRINT_MVFR0 0x02000000 -#define PRINT_MVFR1 0x04000000 -#endif -#define PRINT_CTR_EL0 0x10000000 struct cpu_parts { u_int part_id; @@ -2232,91 +2212,97 @@ print_cpu_features(u_int cpu) "hardware bugs that may cause the incorrect operation of " "atomic operations.\n"); +#define SHOULD_PRINT_REG(_reg) \ + (cpu == 0 || cpu_desc[cpu]._reg != cpu_desc[cpu - 1]._reg) + /* Cache Type Register */ - if (cpu == 0 || (cpu_print_regs & PRINT_CTR_EL0) != 0) { + if (SHOULD_PRINT_REG(ctr)) { print_register(sb, "Cache Type", cpu_desc[cpu].ctr, print_ctr_fields, NULL); } /* AArch64 Instruction Set Attribute Register 0 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR0) != 0) + if (SHOULD_PRINT_REG(id_aa64isar0)) print_id_register(sb, "Instruction Set Attributes 0", cpu_desc[cpu].id_aa64isar0, id_aa64isar0_fields); /* AArch64 Instruction Set Attribute Register 1 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR1) != 0) + if (SHOULD_PRINT_REG(id_aa64isar1)) print_id_register(sb, "Instruction Set Attributes 1", cpu_desc[cpu].id_aa64isar1, id_aa64isar1_fields); /* AArch64 Instruction Set Attribute Register 2 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR2) != 0) + if (SHOULD_PRINT_REG(id_aa64isar2)) print_id_register(sb, "Instruction Set Attributes 2", cpu_desc[cpu].id_aa64isar2, id_aa64isar2_fields); /* AArch64 Processor Feature Register 0 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR0) != 0) + if (SHOULD_PRINT_REG(id_aa64pfr0)) print_id_register(sb, "Processor Features 0", cpu_desc[cpu].id_aa64pfr0, id_aa64pfr0_fields); /* AArch64 Processor Feature Register 1 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR1) != 0) + if (SHOULD_PRINT_REG(id_aa64pfr1)) print_id_register(sb, "Processor Features 1", cpu_desc[cpu].id_aa64pfr1, id_aa64pfr1_fields); /* AArch64 Memory Model Feature Register 0 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR0) != 0) + if (SHOULD_PRINT_REG(id_aa64mmfr0)) print_id_register(sb, "Memory Model Features 0", cpu_desc[cpu].id_aa64mmfr0, id_aa64mmfr0_fields); /* AArch64 Memory Model Feature Register 1 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR1) != 0) + if (SHOULD_PRINT_REG(id_aa64mmfr1)) print_id_register(sb, "Memory Model Features 1", cpu_desc[cpu].id_aa64mmfr1, id_aa64mmfr1_fields); /* AArch64 Memory Model Feature Register 2 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR2) != 0) + if (SHOULD_PRINT_REG(id_aa64mmfr2)) print_id_register(sb, "Memory Model Features 2", cpu_desc[cpu].id_aa64mmfr2, id_aa64mmfr2_fields); /* AArch64 Debug Feature Register 0 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR0) != 0) + if (SHOULD_PRINT_REG(id_aa64dfr0)) print_id_register(sb, "Debug Features 0", cpu_desc[cpu].id_aa64dfr0, id_aa64dfr0_fields); /* AArch64 Memory Model Feature Register 1 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR1) != 0) + if (SHOULD_PRINT_REG(id_aa64dfr1)) print_id_register(sb, "Debug Features 1", cpu_desc[cpu].id_aa64dfr1, id_aa64dfr1_fields); /* AArch64 Auxiliary Feature Register 0 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_AFR0) != 0) + if (SHOULD_PRINT_REG(id_aa64afr0)) print_id_register(sb, "Auxiliary Features 0", cpu_desc[cpu].id_aa64afr0, id_aa64afr0_fields); /* AArch64 Auxiliary Feature Register 1 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_AFR1) != 0) + if (SHOULD_PRINT_REG(id_aa64afr1)) print_id_register(sb, "Auxiliary Features 1", cpu_desc[cpu].id_aa64afr1, id_aa64afr1_fields); /* AArch64 SVE Feature Register 0 */ - /* We check the cpu == 0 case when setting PRINT_ID_AA64_ZFR0 */ - if ((cpu_print_regs & PRINT_ID_AA64_ZFR0) != 0) - print_id_register(sb, "SVE Features 0", - cpu_desc[cpu].id_aa64zfr0, id_aa64zfr0_fields); + if (cpu_desc[cpu].have_sve) { + if (SHOULD_PRINT_REG(id_aa64zfr0) || + !cpu_desc[cpu - 1].have_sve) { + print_id_register(sb, "SVE Features 0", + cpu_desc[cpu].id_aa64zfr0, id_aa64zfr0_fields); + } + } #ifdef COMPAT_FREEBSD32 /* AArch32 Instruction Set Attribute Register 5 */ - if (cpu == 0 || (cpu_print_regs & PRINT_ID_ISAR5) != 0) + if (SHOULD_PRINT_REG(id_isar5)) print_id_register(sb, "AArch32 Instruction Set Attributes 5", cpu_desc[cpu].id_isar5, id_isar5_fields); /* AArch32 Media and VFP Feature Register 0 */ - if (cpu == 0 || (cpu_print_regs & PRINT_MVFR0) != 0) + if (SHOULD_PRINT_REG(mvfr0)) print_id_register(sb, "AArch32 Media and VFP Features 0", cpu_desc[cpu].mvfr0, mvfr0_fields); /* AArch32 Media and VFP Feature Register 1 */ - if (cpu == 0 || (cpu_print_regs & PRINT_MVFR1) != 0) + if (SHOULD_PRINT_REG(mvfr1)) print_id_register(sb, "AArch32 Media and VFP Features 1", cpu_desc[cpu].mvfr1, mvfr1_fields); #endif @@ -2325,6 +2311,7 @@ print_cpu_features(u_int cpu) sbuf_delete(sb); sb = NULL; +#undef SHOULD_PRINT_REG #undef SEP_STR } @@ -2455,61 +2442,11 @@ check_cpu_regs(u_int cpu) break; } - if (cpu_desc[cpu].id_aa64afr0 != cpu_desc[0].id_aa64afr0) - cpu_print_regs |= PRINT_ID_AA64_AFR0; - if (cpu_desc[cpu].id_aa64afr1 != cpu_desc[0].id_aa64afr1) - cpu_print_regs |= PRINT_ID_AA64_AFR1; - - if (cpu_desc[cpu].id_aa64dfr0 != cpu_desc[0].id_aa64dfr0) - cpu_print_regs |= PRINT_ID_AA64_DFR0; - if (cpu_desc[cpu].id_aa64dfr1 != cpu_desc[0].id_aa64dfr1) - cpu_print_regs |= PRINT_ID_AA64_DFR1; - - if (cpu_desc[cpu].id_aa64isar0 != cpu_desc[0].id_aa64isar0) - cpu_print_regs |= PRINT_ID_AA64_ISAR0; - if (cpu_desc[cpu].id_aa64isar1 != cpu_desc[0].id_aa64isar1) - cpu_print_regs |= PRINT_ID_AA64_ISAR1; - if (cpu_desc[cpu].id_aa64isar2 != cpu_desc[0].id_aa64isar2) - cpu_print_regs |= PRINT_ID_AA64_ISAR2; - - if (cpu_desc[cpu].id_aa64mmfr0 != cpu_desc[0].id_aa64mmfr0) - cpu_print_regs |= PRINT_ID_AA64_MMFR0; - if (cpu_desc[cpu].id_aa64mmfr1 != cpu_desc[0].id_aa64mmfr1) - cpu_print_regs |= PRINT_ID_AA64_MMFR1; - if (cpu_desc[cpu].id_aa64mmfr2 != cpu_desc[0].id_aa64mmfr2) - cpu_print_regs |= PRINT_ID_AA64_MMFR2; - - if (cpu_desc[cpu].id_aa64pfr0 != cpu_desc[0].id_aa64pfr0) - cpu_print_regs |= PRINT_ID_AA64_PFR0; - if (cpu_desc[cpu].id_aa64pfr1 != cpu_desc[0].id_aa64pfr1) - cpu_print_regs |= PRINT_ID_AA64_PFR1; - - /* Only print if ID_AA64ZFR0_EL1 is valid */ - if (cpu_desc[cpu].have_sve) { - /* Print if the value changed */ - if (cpu_desc[cpu].id_aa64zfr0 != cpu_desc[0].id_aa64zfr0) { - cpu_print_regs |= PRINT_ID_AA64_ZFR0; - /* Print if it didn't, but the previous CPU was invalid */ - } else if (cpu > 0 && !cpu_desc[cpu - 1].have_sve) { - cpu_print_regs |= PRINT_ID_AA64_ZFR0; - } - } - if (cpu_desc[cpu].ctr != cpu_desc[0].ctr) { /* * If the cache type register is different we may * have a different l1 cache type. */ identify_cache(cpu_desc[cpu].ctr); - cpu_print_regs |= PRINT_CTR_EL0; } - -#ifdef COMPAT_FREEBSD32 - if (cpu_desc[cpu].id_isar5 != cpu_desc[0].id_isar5) - cpu_print_regs |= PRINT_ID_ISAR5; - if (cpu_desc[cpu].mvfr0 != cpu_desc[0].mvfr0) - cpu_print_regs |= PRINT_MVFR0; - if (cpu_desc[cpu].mvfr1 != cpu_desc[0].mvfr1) - cpu_print_regs |= PRINT_MVFR1; -#endif }