From owner-svn-src-head@FreeBSD.ORG Sun Apr 27 20:16:52 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 3BC751A2; Sun, 27 Apr 2014 20:16:52 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 0EA291B18; Sun, 27 Apr 2014 20:16:52 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s3RKGprt023606; Sun, 27 Apr 2014 20:16:51 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s3RKGpMi023604; Sun, 27 Apr 2014 20:16:51 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201404272016.s3RKGpMi023604@svn.freebsd.org> From: Ian Lepore Date: Sun, 27 Apr 2014 20:16:51 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r265024 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 27 Apr 2014 20:16:52 -0000 Author: ian Date: Sun Apr 27 20:16:51 2014 New Revision: 265024 URL: http://svnweb.freebsd.org/changeset/base/265024 Log: Flush and invalidate caches on each CPU as part of handling IPI_STOP. Flushing the caches is required before doing a panic dump, but ARM doesn't provide a flavor of flush that gets broadcast to other cores. However, all cores except one are stopped before doing a dump, so this works around the lack of a global flush/invalidate by doing it locally on each CPU as part of stopping. Discussed with: cognet@ Modified: head/sys/arm/arm/minidump_machdep.c head/sys/arm/arm/mp_machdep.c Modified: head/sys/arm/arm/minidump_machdep.c ============================================================================== --- head/sys/arm/arm/minidump_machdep.c Sun Apr 27 20:01:59 2014 (r265023) +++ head/sys/arm/arm/minidump_machdep.c Sun Apr 27 20:16:51 2014 (r265024) @@ -210,7 +210,15 @@ minidumpsys(struct dumperinfo *di) int i, k, bit, error; char *addr; - /* Flush cache */ + /* + * Flush caches. Note that in the SMP case this operates only on the + * current CPU's L1 cache. Before we reach this point, code in either + * the system shutdown or kernel debugger has called stop_cpus() to stop + * all cores other than this one. Part of the ARM handling of + * stop_cpus() is to call wbinv_all() on that core's local L1 cache. So + * by time we get to here, all that remains is to flush the L1 for the + * current CPU, then the L2. + */ cpu_idcache_wbinv_all(); cpu_l2cache_wbinv_all(); Modified: head/sys/arm/arm/mp_machdep.c ============================================================================== --- head/sys/arm/arm/mp_machdep.c Sun Apr 27 20:01:59 2014 (r265023) +++ head/sys/arm/arm/mp_machdep.c Sun Apr 27 20:16:51 2014 (r265024) @@ -44,6 +44,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include #include @@ -286,6 +287,19 @@ ipi_handler(void *arg) savectx(&stoppcbs[cpu]); + /* + * CPUs are stopped when entering the debugger and at + * system shutdown, both events which can precede a + * panic dump. For the dump to be correct, all caches + * must be flushed and invalidated, but on ARM there's + * no way to broadcast a wbinv_all to other cores. + * Instead, we have each core do the local wbinv_all as + * part of stopping the core. The core requesting the + * stop will do the l2 cache flush after all other cores + * have done their l1 flushes and stopped. + */ + cpu_idcache_wbinv_all(); + /* Indicate we are stopped */ CPU_SET_ATOMIC(cpu, &stopped_cpus);