From owner-freebsd-arm@freebsd.org Thu Sep 8 23:23:48 2016 Return-Path: Delivered-To: freebsd-arm@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 4FBD1BD226D for ; Thu, 8 Sep 2016 23:23:48 +0000 (UTC) (envelope-from e.moe@rcn.com) Received: from smtp.rcn.com (smtp.rcn.com [69.168.97.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id D0B1A9EC for ; Thu, 8 Sep 2016 23:23:47 +0000 (UTC) (envelope-from e.moe@rcn.com) X_CMAE_Category: , , X-CNFS-Analysis: v=2.2 cv=UPOfJ2Xy c=1 sm=1 tr=0 a=dx250bZxW1HngxdpQMIA3g==:117 a=dx250bZxW1HngxdpQMIA3g==:17 a=7Qk2ozbKAAAA:8 a=OA2lqS22AAAA:8 a=c70adeXJmHCkju9f8vMA:9 a=kPP7Z-agIXKUm-HP:21 a=1PZwzYUdmFTMVKzi:21 a=QEXdDO2ut3YA:10 a=27h0jJCSQyChQbBlt5gA:9 a=6rZb-kPnJiAiLgZ4:21 a=fZ-MoroiFIvKbtgA:21 a=sMcuCbCKnVPT6obf:21 a=_W_S_7VecoQA:10 a=cUtMJvZK7BFRT5Nj-HgA:9 a=hquHOILUSkIA:10 a=tclcd6dtLQvEqt9_mmAA:9 a=CjuIK1q_8ugA:10 a=H5KE7-4b7xoaSIFsGHsA:9 a=1lyxoWkJIXJV6VJUPhuM:22 a=047cQLXTEfCjWPUe_kQW:22 X-CM-Score: 0 X-Scanned-by: Cloudmark Authority Engine X-Authed-Username: ZS5tb2VAcmNuLmNvbQ== Authentication-Results: smtp02.rcn.cmh.synacor.com smtp.mail=e.moe@rcn.com; spf=neutral; sender-id=neutral Authentication-Results: smtp02.rcn.cmh.synacor.com header.from=e.moe@rcn.com; sender-id=neutral Authentication-Results: smtp02.rcn.cmh.synacor.com smtp.user=e.moe; auth=pass (PLAIN) Received-SPF: neutral (smtp02.rcn.cmh.synacor.com: 24.148.20.233 is neither permitted nor denied by domain of rcn.com) Received: from [24.148.20.233] ([24.148.20.233:22852] helo=[192.168.3.100]) by smtp.rcn.com (envelope-from ) (ecelerity 3.6.23.54417 r(Core:3.6.23.0)) with ESMTPSA (cipher=DHE-RSA-AES256-SHA) id E2/8F-61435-BF2F1D75; Thu, 08 Sep 2016 19:23:40 -0400 Mime-Version: 1.0 (Mac OS X Mail 9.3 \(3124\)) Subject: Re: Unaligned access in ubldr.bin From: Erik Moe In-Reply-To: Date: Thu, 8 Sep 2016 18:23:39 -0500 Cc: freebsd-arm Message-Id: References: To: Warner Losh , mst@semihalf.com X-Mailer: Apple Mail (2.3124) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Sep 2016 23:23:48 -0000 > On Sep 7, 2016, at 8:22 AM, Warner Losh wrote: >=20 > On Wed, Sep 7, 2016 at 12:46 AM, Erik Moe wrote: >> Hello, >>=20 >> I=E2=80=99ve been trying to bring up FreeBSD on the USB Armory based = on the i.MX53. I=E2=80=99ve made myself a u-boot patch that will load = and start ubldr.bin but I=E2=80=99m running into a issue with what I = think is an unaligned access issue: >=20 > which version of u-boot are you using? I was using 2016.07, but also tried u-boot from head (b615267). >=20 >=20 >> ## Starting application at 0x70800000 ... >> data abort >> pc : [<70824bac>] lr : [<7081846c>] >> sp : 8f550c98 ip : 70835a00 fp : 8f550cb0 >> r10: 00000002 r9 : 70838d58 r8 : 70833cd9 >> r7 : 707fff08 r6 : 000054f0 r5 : 70833cd9 r4 : 00000000 >> r3 : 70828fc4 r2 : 70833cd9 r1 : 00000001 r0 : 7083705c >> Flags: Nzcv IRQs off FIQs off Mode SVC_32 >> Resetting CPU ... >>=20 >> I=E2=80=99ve hand dissambled the code at pc=3D0x70824bac: >>=20 >> 0x70824ba8: 0xe59f21d0 ldr r2, [pc, #464] >> 0x70824bac: 0xe5825000 str r5, [r2] >> 0x70824bb0: 0xe5d53000 ldrb r3, [r5] >> 0x70824bb4: 0xe353002d cmp r3, #45 >> 0x70824bb8: 0x1a00000b bne #+44 >>=20 >> The offending instructions is "str r5, [r2]=E2=80=9D where r2 =3D = 0x70833cd9, which sort of makes sense since it isn=E2=80=99t aligned on = a 4 byte boundary. I=E2=80=99m new to arm ARM, so I=E2=80=99m not = really sure. My questions are these: >>=20 >> 1.) Doesn=E2=80=99t ARMv6 and higher architecture allow unaligned = access? Is there something that u-boot needs be doing in initialization = to allow unaligned access? >=20 > It does, but usually that's configured later in boot. >=20 >> 2.) Does ubldr make the assumption that unaligned access is allowed = and maybe shouldn=E2=80=99t? I would think not since ubldr has been = around for a while and works on numerous ARM processors. >=20 > It may be that the compiler is generating bad code in this case? You > might check to see how we're building it and to see if that's causing > problems. Per Michal Stanek=E2=80=99s suggestion I tried adding = "-mno-unaligned-access=E2=80=9D to the build of ubldr. It=E2=80=99s = still failing in getopt, though not it the same spot: ## Starting application at 0x70800000 ... data abort pc : [<70824bd0>] lr : [<70818454>] sp : 8f559a78 ip : 70835a90 fp : 8f559a90 r10: 00000002 r9 : 70838df0 r8 : 70833d73 r7 : 707fff08 r6 : 00005530 r5 : 70833d73 r4 : 00000000 r3 : 70828fe8 r2 : 70833d73 r1 : 00000001 r0 : 708370ec Flags: Nzcv IRQs off FIQs off Mode SVC_32 Resetting CPU ... 0x70824bcc 0xe59f21d0 ldr r2, [pc, #464] 0x70824bd0 0xe5825000 str r5, [r2] 0x70824bd4 0xe5d53000 ldrb r3, [r5] 0x70824bd8 0xe353002d cmp r3, #45 70833d72: 00 61 3a 00 55 42 6f 6f 74 41 50 49 00 49 44 = .a:.UBootAPI.ID r2 contains 70833d73 which points to =E2=80=9C0x61 0x3a 0x00=E2=80=9D, = which is the literal string =E2=80=9Ca:=E2=80=9D. Looking at the lr = register the calling function is =E2=80=9Capi_parse_cmdline_sig=E2=80=9D. = Looking at the code: api_parse_cmdline_sig(int argc, char **argv, struct api_signature **sig) { unsigned long api_address; int c; api_address =3D 0; opterr =3D 0; optreset =3D 1; optind =3D 1; while ((c =3D getopt (argc, argv, "a:")) !=3D -1) switch (c) { case 'a': api_address =3D strtoul(optarg, NULL, 16); break; default: break; } It=E2=80=99s the third argument to getopt that seems to be on an odd = address. As for the SCTLR.A bit being enabled, that is definitely = something u-boot does, because the default state is for it to be cleared = after reset. I see this in arch/arm/cpu/armv7/start.S: /* * disable MMU stuff and caches */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB #ifdef CONFIG_SYS_ICACHE_OFF bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache #else orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache #endif mcr p15, 0, r0, c1, c0, 0 I tried to clear that flag, but that didn=E2=80=99t work either, but = I=E2=80=99m not sure if this is correct: mac p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00000002 mar p15, 0, r0, c1, c0, 0 Thanks, Erik