Date: Thu, 3 Aug 2023 19:15:14 -0700 From: Mark Millard <marklmi@yahoo.com> To: Konstantin Belousov <kostikbel@gmail.com>, dev-commits-src-main@freebsd.org Subject: Re: git: 5a7e48dddfb5 - main - tests: Add MAP_32BIT flag test Message-ID: <263CA271-1603-41FE-BAF9-E32AC5818945@yahoo.com> References: <263CA271-1603-41FE-BAF9-E32AC5818945.ref@yahoo.com>
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Konstantin Belousov <kostikbel_at_gmail.com> wrote on Date: Thu, 03 Aug 2023 20:58:47 UTC : > On Thu, Aug 03, 2023 at 02:50:57PM +0300, Dmitry Chagin wrote: > > On Wed, Aug 02, 2023 at 12:57:36AM +0300, Konstantin Belousov wrote: > > > On Tue, Aug 01, 2023 at 09:29:32PM +0100, Jessica Clarke wrote: > > > > On 1 Aug 2023, at 21:24, Dmitry Chagin <dchagin@FreeBSD.org> = wrote: > > > > >=20 > > > > > The branch main has been updated by dchagin: > > > > >=20 > > > > > URL: = https://cgit.FreeBSD.org/src/commit/?id=3D5a7e48dddfb5a668ded4742b79e6f6f8= 8b647e6a > > > > >=20 > > > > > commit 5a7e48dddfb5a668ded4742b79e6f6f88b647e6a > > > > > Author: Dmitry Chagin <dchagin@FreeBSD.org> > > > > > AuthorDate: 2023-08-01 20:23:15 +0000 > > > > > Commit: Dmitry Chagin <dchagin@FreeBSD.org> > > > > > CommitDate: 2023-08-01 20:23:15 +0000 > > > > >=20 > > > > > tests: Add MAP_32BIT flag test > > > > >=20 > > > > > Reviewed by: kib, markj > > > > > Differential Revision: https://reviews.freebsd.org/D41236 > > > > > MFC after: 1 month > > > > > --- > > > > > tests/sys/vm/Makefile | 8 ++++++ > > > > > tests/sys/vm/mmap_map_32bit_helper.c | 51 = ++++++++++++++++++++++++++++++++++++ > > > > > tests/sys/vm/mmap_map_32bit_test.sh | 37 = ++++++++++++++++++++++++++ > > > > > 3 files changed, 96 insertions(+) > > > > >=20 > > > > > diff --git a/tests/sys/vm/Makefile b/tests/sys/vm/Makefile > > > > > index 8ef8a45e5f39..9aac49bc5320 100644 > > > > > --- a/tests/sys/vm/Makefile > > > > > +++ b/tests/sys/vm/Makefile > > > > > @@ -9,4 +9,12 @@ ATF_TESTS_C+=3D mlock_test \ > > > > > page_fault_signal \ > > > > > shared_shadow_inval_test > > > > >=20 > > > > > +.if ${MACHINE_ARCH} !=3D "i386" && ${MACHINE} !=3D "arm" && \ > > > > > + (${MACHINE} !=3D "powerpc" || ${MACHINE_ARCH} !=3D = "powerpc") > > > > > + # MAP_32BIT is only available on 64-bit platforms > > > >=20 > > > > So use ${MACHINE_ABI:Mlong64} after including src.opts.mk? > > >=20 > > > May be we should enable the MAP_32BIT flag on 32bit arches, = instead? > > > It requests allocation below 2G, which is half of VA on i386, or = 2/3 > > > on arm. Interestingly, it should work already from compat32. > >=20 > > It's disturbing that no none has requested this, I can do that > Please do. The largest part of the work is to recheck the man page and = tests. If I guess correctly, the above implies restricting the process size on native armv7 to a strict 2 GiBytes or so. The OrangePi+2Ed (cortex-a7) that I use has a somewhat larger effective process address space (RAM+SWAP usable by one process) than the armv7 chroot/jail use on any of the = cortex-a72/cortex-a53/cortex-x1c/cortex-a78c aarch64 systems that I've access to. I have actually built something on the OrangePi+2Ed that I could not build on the aarch64 systems in an = armv7 poudriere-devel jail --because of the process size limitation on aarch64 systems was smaller. (Not that I remember the details. I do not do such builds regularly. But I might have notes about it someplace.) So a ~2 GiByte process size limitation would make armv7 = chroot/jail/lib32=20 on aarch64 vs. native armv7 more uniform --but some native armv7's could be somewhat less capable. Note: It is not obvious to me that keeping armv7 going until FreeBSD = 15's release avoids being too restrictive, even as tier 2. Even the somewhat larger address space for native could easily end up being too much of a constraint, for example, much like the process size build problems that happen now for armv7 on aarch64 for port builds in poudriere(-devel) jails. For reference: CPU: ARM Cortex-A7 r0p5 (ECO: 0x00000000) CPU Features:=20 Multiprocessing, Thumb2, Security, Virtualization, Generic Timer, = VMSAv7, PXN, LPAE, Coherent Walk Optional instructions:=20 SDIV/UDIV, UMULL, SMULL, SIMD(ext) LoUU:2 LoC:3 LoUIS:2=20 Cache level 1: 32KB/64B 4-way data cache WB Read-Alloc Write-Alloc 32KB/32B 2-way instruction cache Read-Alloc Cache level 2: 512KB/64B 8-way unified cache WB Read-Alloc Write-Alloc real memory =3D 2113257472 (2015 MB) avail memory =3D 2054692864 (1959 MB) =3D=3D=3D Mark Millard marklmi at yahoo.com
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