From owner-svn-src-head@FreeBSD.ORG Mon Apr 28 02:35:29 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 56C35CD9; Mon, 28 Apr 2014 02:35:29 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4461A1B73; Mon, 28 Apr 2014 02:35:29 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s3S2ZT6o079206; Mon, 28 Apr 2014 02:35:29 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s3S2ZTGN079205; Mon, 28 Apr 2014 02:35:29 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201404280235.s3S2ZTGN079205@svn.freebsd.org> From: Ian Lepore Date: Mon, 28 Apr 2014 02:35:29 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r265036 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Apr 2014 02:35:29 -0000 Author: ian Date: Mon Apr 28 02:35:28 2014 New Revision: 265036 URL: http://svnweb.freebsd.org/changeset/base/265036 Log: Don't use multiprocessing-extensions instruction on processors that don't support SMP. Submitted by: loos@ Pointy hat to: me Modified: head/sys/arm/arm/cpufunc_asm_armv7.S Modified: head/sys/arm/arm/cpufunc_asm_armv7.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_armv7.S Sun Apr 27 23:47:38 2014 (r265035) +++ head/sys/arm/arm/cpufunc_asm_armv7.S Mon Apr 28 02:35:28 2014 (r265036) @@ -251,7 +251,11 @@ ENTRY(armv7_idcache_wbinv_range) END(armv7_idcache_wbinv_range) ENTRY_NP(armv7_icache_sync_all) +#ifdef SMP mcr p15, 0, r0, c7, c1, 0 /* Invalidate all I cache to PoU Inner Shareable */ +#else + mcr p15, 0, r0, c7, c5, 0 /* Invalidate all I cache to PoU (ICIALLU) */ +#endif isb /* instruction synchronization barrier */ dsb /* data synchronization barrier */ RET