Date: Thu, 17 Jan 2019 23:27:38 +0000 From: bugzilla-noreply@freebsd.org To: ports-bugs@FreeBSD.org Subject: [Bug 230761] New port: cad/verilator: fastest free Verilog HDL simulator Message-ID: <bug-230761-7788-I514Xr3DcF@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-230761-7788@https.bugs.freebsd.org/bugzilla/> References: <bug-230761-7788@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D230761 --- Comment #3 from commit-hook@freebsd.org --- A commit references this bug: Author: swills Date: Thu Jan 17 23:27:12 UTC 2019 New revision: 490609 URL: https://svnweb.freebsd.org/changeset/ports/490609 Log: cad/verilator: create port Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It = is designed for large projects where fast simulation performance is of prima= ry concern, and is especially well suited to generate executable models of C= PUs for embedded software design teams. WWW: https://www.veripool.org/projects/verilator/wiki/Intro PR: 230761 Submitted by: Kevin Zheng <kevinz5000@gmail.com> Changes: head/cad/Makefile head/cad/verilator/ head/cad/verilator/Makefile head/cad/verilator/distinfo head/cad/verilator/pkg-descr head/cad/verilator/pkg-plist --=20 You are receiving this mail because: You are the assignee for the bug.=
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