From owner-svn-src-head@freebsd.org Wed Jan 20 13:55:53 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 81A03A8999C; Wed, 20 Jan 2016 13:55:53 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 433CA1597; Wed, 20 Jan 2016 13:55:53 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u0KDtqjR068649; Wed, 20 Jan 2016 13:55:52 GMT (envelope-from zbb@FreeBSD.org) Received: (from zbb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u0KDtq0S068646; Wed, 20 Jan 2016 13:55:52 GMT (envelope-from zbb@FreeBSD.org) Message-Id: <201601201355.u0KDtq0S068646@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: zbb set sender to zbb@FreeBSD.org using -f From: Zbigniew Bodek Date: Wed, 20 Jan 2016 13:55:52 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r294426 - in head/sys/arm/mv: . armada38x X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jan 2016 13:55:53 -0000 Author: zbb Date: Wed Jan 20 13:55:51 2016 New Revision: 294426 URL: https://svnweb.freebsd.org/changeset/base/294426 Log: Enable SCU unit for Armada38x Valid SCU operation is necessary for SMP interoperability. Initialization function armada38x_enable_scu() was added. Reviewed by: andrew, ian Obtained from: Semihalf Sponsored by: Stormshield Submitted by: Bartosz Szczepanek Differential revision: https://reviews.freebsd.org/D4220 Modified: head/sys/arm/mv/armada38x/armada38x.c head/sys/arm/mv/mv_machdep.c head/sys/arm/mv/mvreg.h Modified: head/sys/arm/mv/armada38x/armada38x.c ============================================================================== --- head/sys/arm/mv/armada38x/armada38x.c Wed Jan 20 13:53:33 2016 (r294425) +++ head/sys/arm/mv/armada38x/armada38x.c Wed Jan 20 13:55:51 2016 (r294426) @@ -39,6 +39,7 @@ __FBSDID("$FreeBSD$"); #include int armada38x_win_set_iosync_barrier(void); +int armada38x_scu_enable(void); uint32_t get_tclk(void) @@ -78,3 +79,25 @@ armada38x_win_set_iosync_barrier(void) return (rv); } + +int +armada38x_scu_enable(void) +{ + bus_space_handle_t vaddr_scu; + int rv; + uint32_t val; + + rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE, + MV_SCU_REGS_LEN, 0, &vaddr_scu); + if (rv != 0) + return (rv); + + /* Enable SCU */ + val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CTRL); + if (!(val & MV_SCU_ENABLE)) + bus_space_write_4(fdtbus_bs_tag, vaddr_scu, 0, + val | MV_SCU_ENABLE); + + bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN); + return (0); +} Modified: head/sys/arm/mv/mv_machdep.c ============================================================================== --- head/sys/arm/mv/mv_machdep.c Wed Jan 20 13:53:33 2016 (r294425) +++ head/sys/arm/mv/mv_machdep.c Wed Jan 20 13:55:51 2016 (r294426) @@ -68,6 +68,7 @@ void armadaxp_l2_init(void); #endif #if defined(SOC_MV_ARMADA38X) int armada38x_win_set_iosync_barrier(void); +int armada38x_scu_enable(void); #endif #define MPP_PIN_MAX 68 @@ -257,6 +258,8 @@ platform_late_init(void) /* Set IO Sync Barrier bit for all Mbus devices */ if (armada38x_win_set_iosync_barrier() != 0) printf("WARNING: could not map CPU Subsystem registers\n"); + if (armada38x_scu_enable() != 0) + printf("WARNING: could not enable SCU\n"); #endif } Modified: head/sys/arm/mv/mvreg.h ============================================================================== --- head/sys/arm/mv/mvreg.h Wed Jan 20 13:53:33 2016 (r294425) +++ head/sys/arm/mv/mvreg.h Wed Jan 20 13:55:51 2016 (r294426) @@ -34,6 +34,8 @@ #ifndef _MVREG_H_ #define _MVREG_H_ +#include + #if defined(SOC_MV_DISCOVERY) #define IRQ_CAUSE_ERROR 0x0 #define IRQ_CAUSE 0x4 @@ -452,4 +454,15 @@ #define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) #define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) #endif + +/* + * SCU + */ +#if defined(SOC_MV_ARMADA38X) +#define MV_SCU_BASE (MV_BASE + 0xc000) +#define MV_SCU_REGS_LEN 0x100 +#define MV_SCU_REG_CTRL 0 +#define MV_SCU_ENABLE 1 +#endif + #endif /* _MVREG_H_ */