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Date:      Tue, 03 Apr 2018 13:15:30 +0000
From:      bugzilla-noreply@freebsd.org
To:        freebsd-ports-bugs@FreeBSD.org
Subject:   [Bug 227254] [New Port] devel/abc: System for Sequential Synthesis and Verification
Message-ID:  <bug-227254-13@https.bugs.freebsd.org/bugzilla/>

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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D227254

            Bug ID: 227254
           Summary: [New Port] devel/abc: System for Sequential Synthesis
                    and Verification
           Product: Ports & Packages
           Version: Latest
          Hardware: Any
                OS: Any
            Status: New
          Severity: Affects Only Me
          Priority: ---
         Component: Individual Port(s)
          Assignee: freebsd-ports-bugs@FreeBSD.org
          Reporter: uddka@student.kit.edu

Created attachment 192167
  --> https://bugs.freebsd.org/bugzilla/attachment.cgi?id=3D192167&action=
=3Dedit
shar archive of devel/abc

ABC is a growing software system for synthesis and verification of binary
sequential logic circuits appearing in synchronous hardware designs. ABC
combines scalable logic optimization based on And-Inverter Graphs (AIGs),
optimal-delay DAG-based technology mapping for look-up tables and standard
cells, and innovative algorithms for sequential synthesis and verification.

ABC provides an experimental implementation of these algorithms and a
programming environment for building similar applications. Future developme=
nt
will focus on improving the algorithms and making most of the packages
stand-alone. This will allow the user to customize ABC for their needs as if
it were a tool-box rather than a complete tool.

WWW: https://people.eecs.berkeley.edu/~alanmi/abc/

portlint: looks fine.
poudriere: build successful.

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