From owner-svn-src-head@freebsd.org Fri Jul 27 15:31:21 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 6D6C7104E8B0; Fri, 27 Jul 2018 15:31:21 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 237207A1EE; Fri, 27 Jul 2018 15:31:21 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 0641019B6F; Fri, 27 Jul 2018 15:31:21 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w6RFVKYv021506; Fri, 27 Jul 2018 15:31:20 GMT (envelope-from kib@FreeBSD.org) Received: (from kib@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w6RFVK57021504; Fri, 27 Jul 2018 15:31:20 GMT (envelope-from kib@FreeBSD.org) Message-Id: <201807271531.w6RFVK57021504@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: kib set sender to kib@FreeBSD.org using -f From: Konstantin Belousov Date: Fri, 27 Jul 2018 15:31:20 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r336763 - in head/sys: amd64/amd64 x86/x86 X-SVN-Group: head X-SVN-Commit-Author: kib X-SVN-Commit-Paths: in head/sys: amd64/amd64 x86/x86 X-SVN-Commit-Revision: 336763 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jul 2018 15:31:21 -0000 Author: kib Date: Fri Jul 27 15:31:20 2018 New Revision: 336763 URL: https://svnweb.freebsd.org/changeset/base/336763 Log: On amd64, enable workarounds for several Ryzen erratas as described in the AMD document 55449 'Revision Guide for AMD Family 17h Models 00h-0Fh Processors' rev 1.12. The errata numbers are mentioned near each action. It seems that newer BIOSes already include required chicken bits settings, so the magic MSR updates are only needed when BIOS cannot be updated. On the other hand, MWAIT avoidance seems to be important. Sponsored by: The FreeBSD Foundation MFC after: 1 week Modified: head/sys/amd64/amd64/initcpu.c head/sys/x86/x86/cpu_machdep.c Modified: head/sys/amd64/amd64/initcpu.c ============================================================================== --- head/sys/amd64/amd64/initcpu.c Fri Jul 27 15:17:24 2018 (r336762) +++ head/sys/amd64/amd64/initcpu.c Fri Jul 27 15:31:20 2018 (r336763) @@ -130,6 +130,30 @@ init_amd(void) } } + /* Ryzen erratas. */ + if (CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1 && + (cpu_feature2 & CPUID2_HV) == 0) { + /* 1021 */ + msr = rdmsr(0xc0011029); + msr |= 0x2000; + wrmsr(0xc0011029, msr); + + /* 1033 */ + msr = rdmsr(0xc0011020); + msr |= 0x10; + wrmsr(0xc0011020, msr); + + /* 1049 */ + msr = rdmsr(0xc0011028); + msr |= 0x10; + wrmsr(0xc0011028, msr); + + /* 1095 */ + msr = rdmsr(0xc0011020); + msr |= 0x200000000000000; + wrmsr(0xc0011020, msr); + } + /* * Work around a problem on Ryzen that is triggered by executing * code near the top of user memory, in our case the signal Modified: head/sys/x86/x86/cpu_machdep.c ============================================================================== --- head/sys/x86/x86/cpu_machdep.c Fri Jul 27 15:17:24 2018 (r336762) +++ head/sys/x86/x86/cpu_machdep.c Fri Jul 27 15:31:20 2018 (r336763) @@ -709,6 +709,13 @@ cpu_idle_tun(void *unused __unused) if (TUNABLE_STR_FETCH("machdep.idle", tunvar, sizeof(tunvar))) cpu_idle_selector(tunvar); + else if (cpu_vendor_id == CPU_VENDOR_AMD && + CPUID_TO_FAMILY(cpu_id) == 0x17 && CPUID_TO_MODEL(cpu_id) == 0x1) { + /* Ryzen erratas 1057, 1109. */ + cpu_idle_selector("hlt"); + idle_mwait = 0; + } + if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_id == 0x506c9) { /* * Apollo Lake errata APL31 (public errata APL30).