From owner-freebsd-arm@freebsd.org Wed Aug 26 14:22:11 2015 Return-Path: Delivered-To: freebsd-arm@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id E4BE89C318F for ; Wed, 26 Aug 2015 14:22:11 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from outbound1b.ore.mailhop.org (outbound1b.ore.mailhop.org [54.200.247.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id BC80BC0C for ; Wed, 26 Aug 2015 14:22:11 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from ilsoft.org (unknown [73.34.117.227]) by outbound1.ore.mailhop.org (Halon Mail Gateway) with ESMTPSA; Wed, 26 Aug 2015 14:21:09 +0000 (UTC) Received: from rev (rev [172.22.42.240]) by ilsoft.org (8.14.9/8.14.9) with ESMTP id t7QEL2A5021524; Wed, 26 Aug 2015 08:21:03 -0600 (MDT) (envelope-from ian@freebsd.org) Message-ID: <1440598862.1313.45.camel@freebsd.org> Subject: Re: DWC OTG TX path optimisation for 11-current From: Ian Lepore To: Hans Petter Selasky Cc: freebsd-arm@FreeBSD.org Date: Wed, 26 Aug 2015 08:21:02 -0600 In-Reply-To: <55DD5C0A.2050401@selasky.org> References: <55A7D8CE.4020809@selasky.org> <55B23276.8090703@selasky.org> <55B73113.2020308@selasky.org> <55B8AB76.7030603@selasky.org> <55B8B297.1010008@selasky.org> <20150729154516.GH78154@funkthat.com> <55B8F5EC.2050908@selasky.org> <46ad096c958.1a82a175@mail.schwarzes.net> <55B9C3E2.5040501@selasky.org> <46ae815c7c3.447237c8@mail.schwarzes.net> <46aece00b53.3c1cdc1f@mail.schwarzes.net> <55BB2A5F.9000502@selasky.org> <46baa16c4ce.6efd29ef@mail.schwarzes.net> <55CF31A1.5080205@selasky.org> <46ce372c895.20050775@mail.schwarzes.net> <46d0a4441bb.41f6f91d@mail.schwarzes.net> <55DD5C0A.2050401@selasky.org> Content-Type: text/plain; charset="us-ascii" X-Mailer: Evolution 3.12.10 FreeBSD GNOME Team Port Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Aug 2015 14:22:12 -0000 On Wed, 2015-08-26 at 08:26 +0200, Hans Petter Selasky wrote: > On 08/25/15 21:51, Andreas Schwarz wrote: > > On 24.08.15, Andreas Schwarz wrote: > > > >> With both kernels I was not able to reproduce the initial problem. > > > > By accident, today I run again into the problem (with r287086). 8( > > > > Aug 25 20:27:59 pizelot kernel: smsc0: warning: Failed to write register 0x114 > > Aug 25 20:45:32 pizelot kernel: smsc0: warning: Failed to read register 0x114 > > Aug 25 20:45:32 pizelot kernel: smsc0: warning: MII is busy > > Aug 25 20:46:08 pizelot kernel: smsc0: warning: Failed to write register 0x114 > > Aug 25 20:46:14 pizelot kernel: smsc0: warning: Failed to read register 0x114 > > Aug 25 20:46:14 pizelot kernel: smsc0: warning: MII is busy > > Aug 25 20:46:16 pizelot kernel: smsc0: warning: Failed to write register 0x114 > > Aug 25 20:46:46 pizelot kernel: smsc0: warning: Failed to read register 0x114 > > Aug 25 20:46:46 pizelot kernel: smsc0: warning: MII is busy > > [...] > > > > It might seem like some process is using all CPU on core 0, so that USB > doesn't get a chance to run. I would suggest maybe moving the DWC OTG > fast IRQ handling to core #1. Is it possible you could enter kgdb, and > poke around which fast IRQ is doing work there? > All interrupt handlers on armv6 run on core 0, always. There's no way to change that. -- Ian